diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-07-28 11:32:21 -0600 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2021-09-20 15:44:09 +0000 |
| commit | ff8d0e64a7b3b60f646014523054eb96ec919112 (patch) | |
| tree | 86769f6f84ced80759164b1df5cc5837f2b32a5b | |
| parent | e186821952ad7e2248d63ba21041fe84f756816e (diff) | |
| download | coreboot-ff8d0e64a7b3b60f646014523054eb96ec919112.tar.gz coreboot-ff8d0e64a7b3b60f646014523054eb96ec919112.tar.bz2 coreboot-ff8d0e64a7b3b60f646014523054eb96ec919112.zip | |
soc/intel/jasperlake: Clear RTC_BATTERY_DEAD
Normally for vboot-enabled x86 board, the VBNV region is stored in CMOS
and backed up to flash (RW_NVRAM). However, on the very first boot after
a flash of the full SPI image (so RW_NVRAM is empty), if
RTC_BATTERY_DEAD is set, coreboot persistently requests recovery before
FSP-M finishes (which appears to be the current location that
RTC_BATTERY_DEAD is cleared on this platform). This is because
vbnv_cmos_failed() will still return 1. Therefore, immediately after
reading RTC_BATTERY_DEAD, it is cleared. This prevents an infinite boot
loop when trying to set the recovery mode bit.
Note that this was the behavior for previous generations of Intel PMC
programming as well (see southbridge/intel, soc/skylake, soc/broadwell,
etc).
BUG=b:181678769
Change-Id: Idfaa9a24f7b7fefa4f63ab8e3bc4ee6a0f1faedf
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
| -rw-r--r-- | src/soc/intel/jasperlake/pmutil.c | 20 |
1 files changed, 18 insertions, 2 deletions
diff --git a/src/soc/intel/jasperlake/pmutil.c b/src/soc/intel/jasperlake/pmutil.c index 4d9a12364138..d9ecb6332d32 100644 --- a/src/soc/intel/jasperlake/pmutil.c +++ b/src/soc/intel/jasperlake/pmutil.c @@ -178,6 +178,22 @@ static int rtc_failed(uint32_t gen_pmcon_b) return !!(gen_pmcon_b & RTC_BATTERY_DEAD); } +static void clear_rtc_failed(void) +{ + clrbits8(pmc_mmio_regs() + GEN_PMCON_B, RTC_BATTERY_DEAD); +} + +static int check_rtc_failed(uint32_t gen_pmcon_b) +{ + const int failed = rtc_failed(gen_pmcon_b); + if (failed) { + clear_rtc_failed(); + printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", failed); + } + + return failed; +} + int soc_get_rtc_failed(void) { const struct chipset_power_state *ps; @@ -185,12 +201,12 @@ int soc_get_rtc_failed(void) if (acpi_pm_state_for_rtc(&ps) < 0) return 1; - return rtc_failed(ps->gen_pmcon_b); + return check_rtc_failed(ps->gen_pmcon_b); } int vbnv_cmos_failed(void) { - return rtc_failed(read32(pmc_mmio_regs() + GEN_PMCON_B)); + return check_rtc_failed(read32(pmc_mmio_regs() + GEN_PMCON_B)); } static inline int deep_s3_enabled(void) |