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| author | Subrata Banik <subratabanik@google.com> | 2023-01-16 15:16:26 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-01-18 11:51:07 +0000 |
| commit | ffa5ff84702684af7496ce8ad962e0f1c8b060cd (patch) | |
| tree | 3cd101f0b02bdae0ed657a02231c2a8098804368 | |
| parent | a5a357ca10f3c485f8269a5d8acac9c1851a0720 (diff) | |
| download | coreboot-ffa5ff84702684af7496ce8ad962e0f1c8b060cd.tar.gz coreboot-ffa5ff84702684af7496ce8ad962e0f1c8b060cd.tar.bz2 coreboot-ffa5ff84702684af7496ce8ad962e0f1c8b060cd.zip | |
soc/intel/icelake: Fix incorrect `prev_sleep_state` issue
The patch fixes indication of incorrect `prev_sleep_state` on the next
boot after global reset trigger. The existing code misses an important check about `if PCH doesn't set the WAK_STS` while checking power
failure. As a result, every early warm/global reset is considered
as power failure after looking into the PMC MMIO CON-A register
alone (as ignoring the ACPI PM_CTRL.WAK_STS bit).
As per the code comment this code logic is expected to check the power
failure reason if PCH doesn't set the WAK_STS while waking from G3
state.
TEST=Able to build and boot google/dragonegg.
Without this patch:
Observation: Resuming after a warm reset is considered as
`prev_sleep_state 5` although the SLP_TYP is zero and WAK_STS bit
is set.
pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000
GEN_PMCON: d1215238 00002200
....
prev_sleep_state 5
With this patch:
Observation: Resuming after a warm reset is considered as
`prev_sleep_state 0`. It matches with the SLP_TYP is zero and
WAK_STS bit is set.
pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000
GEN_PMCON: d1215238 00002200
....
prev_sleep_state 0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I0e5a6e54abc7c03a2fbffa308db20c392e2a600b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71983
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/icelake/pmutil.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c index 306709d4dc33..9f7b72c718c2 100644 --- a/src/soc/intel/icelake/pmutil.c +++ b/src/soc/intel/icelake/pmutil.c @@ -211,7 +211,7 @@ int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_st * S5 because the PCH does not set the WAK_STS bit when waking * from a true G3 state. */ - if (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR)) + if (!(ps->pm1_sts & WAK_STS) && (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR))) prev_sleep_state = ACPI_S5; /* |