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| author | Edward O'Callaghan <quasisec@google.com> | 2020-01-21 21:01:32 +1100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-01-30 11:46:23 +0000 |
| commit | b765fa6e4789a160cd3fc543e6f659c333a17110 (patch) | |
| tree | 9126d77ff30e4abd79c0e81c1af20abf71b5e53b /AUTHORS | |
| parent | 7e2625587d11209bdecbeffda3267b2336477b78 (diff) | |
| download | coreboot-b765fa6e4789a160cd3fc543e6f659c333a17110.tar.gz coreboot-b765fa6e4789a160cd3fc543e6f659c333a17110.tar.bz2 coreboot-b765fa6e4789a160cd3fc543e6f659c333a17110.zip | |
drivers/net/r8168: Add SSDT Power Resource Methods
Turns out when going into S0ix we want the kernel to toggle de-assert to 0 for
the ISOLATE# pin on the NIC for S0ix not to be woken by PCIe traffic on PCH.
Upon resume the ISOLATE# pin on the NIC is then re-asserted for it to become
lively again.
V.2: Ensure reset_gpio && enable_gpio are optional.
BUG=b:147026979
BRANCH=none
TEST=Boot puff and do 100 cycles of S0ix.
Change-Id: I3ae8dc30f45f55eec23f45e7b5fbc67a4542f87d
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'AUTHORS')
0 files changed, 0 insertions, 0 deletions