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authorPaul Menzel <pmenzel@molgen.mpg.de>2020-05-10 22:00:42 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-05-12 19:41:43 +0000
commit3b3512941b557e1b8c0eb1922fa762f225848344 (patch)
tree0e4e1172cd3aee12692616b8a65aeddf2cf1e74a /Documentation/getting_started
parent5e64f01e791825a866a51919cd006de6512389df (diff)
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Documentation/getting_started: Fix typo
Change-Id: I41571c45719dfade49a021b6bafe80afdcb7b581 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41223 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'Documentation/getting_started')
-rw-r--r--Documentation/getting_started/architecture.md2
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/getting_started/architecture.md b/Documentation/getting_started/architecture.md
index d037f752d967..8d63ac2c75e5 100644
--- a/Documentation/getting_started/architecture.md
+++ b/Documentation/getting_started/architecture.md
@@ -10,7 +10,7 @@ coreboot consists of multiple stages that are compiled as separate binaries and
are inserted into the CBFS with custom compression. The bootblock usually doesn't
have compression while the ramstage and payload are compressed with LZMA.
-Each stage loads the next stage a given address (possibly decompressing it).
+Each stage loads the next stage at given address (possibly decompressing it).
Some stages are relocatable and can be placed anywhere in DRAM. Those stages are
usually cached in CBMEM for faster loading times on ACPI S3 resume.