diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2021-01-14 00:09:11 +0100 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2021-01-23 09:23:23 +0000 |
| commit | d509ee55b6b91270b1369311e20cbc717ad7b4b4 (patch) | |
| tree | 2b0ebaac48083f3dd9d78ac546bf489091c251da /Documentation/getting_started | |
| parent | d5ab1267e5f7123d3ce3e5f87fca0aef845f670b (diff) | |
| download | coreboot-d509ee55b6b91270b1369311e20cbc717ad7b4b4.tar.gz coreboot-d509ee55b6b91270b1369311e20cbc717ad7b4b4.tar.bz2 coreboot-d509ee55b6b91270b1369311e20cbc717ad7b4b4.zip | |
soc/intel/apl: drop LPC pad configuration code
Drop LPC pad configuration code since all boards now do pad
configuration on their own. The comment about LPC_CLKRUNB when using
eSPI is moved to `Documentation/getting_started/gpio.md`.
Change-Id: I710d6aee8c3b2c8282cd321cd0688b9b26abea07
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49410
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'Documentation/getting_started')
| -rw-r--r-- | Documentation/getting_started/gpio.md | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/Documentation/getting_started/gpio.md b/Documentation/getting_started/gpio.md index 13aeed5bd2ab..d4e8ca7df40a 100644 --- a/Documentation/getting_started/gpio.md +++ b/Documentation/getting_started/gpio.md @@ -129,3 +129,13 @@ If no pullup or pulldown is declared with these, they may end up "floating", i.e., not at logical high or logical low. This can cause problems such as unwanted power consumption or not reading the pin correctly, if it was intended to be strapped. + +## Pad-related known issues and workarounds + +### LPC_CLKRUNB blocks S0ix states when board uses eSPI + +When using eSPI, the pad implementing `LPC_CLKRUNB` must be set to GPIO mode. +Other pin settings i.e. Rx path enable/disable, Tx path enable/disable, pull up +enable/disable etc are ignored. Leaving this pin in native mode will keep the +LPC Controller awake and prevent S0ix entry. This issues is know at least on +Apollolake and Geminilake. |