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| author | Arthur Heymans <arthur@aheymans.xyz> | 2020-11-12 21:19:46 +0100 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2020-11-20 10:18:57 +0000 |
| commit | 3622c0bf10ef273c7b530879d1a1af738d65ae66 (patch) | |
| tree | 3b9ca4cba6de3365f2077a423e8c552e2600cad5 /Documentation/mainboard/51nb | |
| parent | 3d802535cbf222d403e0d7d5cc6632546333a4c4 (diff) | |
| download | coreboot-3622c0bf10ef273c7b530879d1a1af738d65ae66.tar.gz coreboot-3622c0bf10ef273c7b530879d1a1af738d65ae66.tar.bz2 coreboot-3622c0bf10ef273c7b530879d1a1af738d65ae66.zip | |
soc/intel/xeon_sp/cpx: Modify PCH_IOAPIC_BUS_NUMBER
The PCH IOAPIC is not PCI discoverable.
Linux checks the BDF set in DMAR against the PCI class if it is a PIC,
which 00:1F.0 for instance isn't.
The SINIT ACM on the other hand bails out with ERROR CLASS:0xA, MAJOR
3, MINOR 7 if the BUS number is 0.
Change-Id: I9b8d35a66762247fde698e459e30ce4c8a2c7eb0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Diffstat (limited to 'Documentation/mainboard/51nb')
0 files changed, 0 insertions, 0 deletions