mainboard/protectli/vault_ehl: Add initial structure

This patch adds base code for the Protectli VP2420. The GPIO
config has been extracted with inteltool from the stock
firmware and then parsed with intelp2m. As of now, the platform
runs with edk2 with no apparent issues.

Signed-off-by: Kacper Stojek <kacper.stojek@3mdeb.com>
Signed-off-by: Artur Kowalski <artur.kowalski@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Change-Id: Ia00c27117d48b76db306d3f988f159fc5d50e4a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>

5 files changed, 88 insertions, 0 deletions

diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index 2257059a2a57..a1cd9f57c1b1 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -168,6 +168,7 @@ The boards in this section are not real mainboards, but emulators.
 
 - [FW2B / FW4B](protectli/fw2b_fw4b.md)
 - [FW6A / FW6B / FW6C](protectli/fw6.md)
+- [VP2420](protectli/vp2420.md)
 - [VP4630 / VP4650 / VP4670](protectli/vp46xx.md)
 
 ## Roda
diff --git a/Documentation/mainboard/protectli/VP2420_back.jpg b/Documentation/mainboard/protectli/VP2420_back.jpg
new file mode 100644
index 000000000000..eaeb04beab2e
--- /dev/null
+++ b/Documentation/mainboard/protectli/VP2420_back.jpg
diff --git a/Documentation/mainboard/protectli/VP2420_front.jpg b/Documentation/mainboard/protectli/VP2420_front.jpg
new file mode 100644
index 000000000000..fdac4d19b0bb
--- /dev/null
+++ b/Documentation/mainboard/protectli/VP2420_front.jpg
diff --git a/Documentation/mainboard/protectli/VP2420_internal.jpg b/Documentation/mainboard/protectli/VP2420_internal.jpg
new file mode 100644
index 000000000000..bc9c2cd0196b
--- /dev/null
+++ b/Documentation/mainboard/protectli/VP2420_internal.jpg
diff --git a/Documentation/mainboard/protectli/vp2420.md b/Documentation/mainboard/protectli/vp2420.md
new file mode 100644
index 000000000000..68b5da0d6178
--- /dev/null
+++ b/Documentation/mainboard/protectli/vp2420.md
@@ -0,0 +1,87 @@
+# Protectli Vault VP2420
+
+This page describes how to run coreboot on the [Protectli VP2420].
+
+![](VP2420_back.jpg)
+![](VP2420_front.jpg)
+
+## Required proprietary blobs
+
+To build a minimal working coreboot image some blobs are required (assuming
+only the BIOS region is being modified).
+
+```eval_rst
++-----------------+---------------------------------+---------------------+
+| Binary file     | Apply                           | Required / Optional |
++=================+=================================+=====================+
+| FSP-M, FSP-S    | Intel Firmware Support Package  | Required            |
++-----------------+---------------------------------+---------------------+
+| microcode       | CPU microcode                   | Required            |
++-----------------+---------------------------------+---------------------+
+```
+
+FSP-M and FSP-S are obtained after splitting the Elkhart Lake FSP binary (done
+automatically by the coreboot build system and included into the image) from
+the `3rdparty/fsp` submodule.
+
+Microcode updates are automatically included into the coreboot image by build
+system from the `3rdparty/intel-microcode` submodule.
+
+## Flashing coreboot
+
+### Internal programming
+
+The main SPI flash can be accessed using [flashrom]. Firmware can be easily
+flashed with internal programmer (either BIOS region or full image).
+
+### External programming
+
+The system has an internal flash chip which is a 16 MiB soldered SOIC-8 chip.
+This chip is located on the top side of the case (the lid side). One has to
+remove 4 top cover screws and lift up the lid. The flash chip is soldered in
+under RAM, easily accessed after taking out the memory. Specifically, it's a
+KH25L12835F (3.3V) which is a clone of Macronix
+MX25L12835F - [datasheet][MX25L12835F].
+
+![](VP2420_internal.jpg)
+
+## Working
+
+- USB 3.0 front ports (SeaBIOS, Tianocore UEFIPayload and Linux)
+- 4 Ethernet ports
+- HDMI, DisplayPort
+- flashrom
+- M.2 WiFi
+- M.2 4G LTE
+- M.2 SATA and NVMe
+- 2.5'' SATA SSD
+- eMMC
+- Super I/O serial port 0 via front microUSB connector
+- SMBus (reading SPD from DIMMs)
+- Initialization with Elkhart Lake FSP 2.0
+- SeaBIOS payload (version rel-1.16.0)
+- TianoCore UEFIPayload
+- Reset switch
+- Booting Debian, Ubuntu, FreeBSD
+
+## Technology
+
+```eval_rst
++------------------+--------------------------------------------------+
+| CPU              | Intel Celeron J6412                              |
++------------------+--------------------------------------------------+
+| PCH              | Intel Elkhart Lake                               |
++------------------+--------------------------------------------------+
+| Super I/O, EC    | ITE IT8613E                                      |
++------------------+--------------------------------------------------+
+| Coprocessor      | Intel Management Engine                          |
++------------------+--------------------------------------------------+
+```
+
+## Useful links
+
+- [VP2420 Hardware Overview](https://protectli.com/kb/vp2400-series-hardware-overview/)
+- [VP2420 Product Page](https://protectli.com/product/vp2420/)
+- [Protectli TPM module](https://protectli.com/product/tpm-module/)
+- [MX25L12835F](https://www.mxic.com.tw/Lists/Datasheet/Attachments/8653/MX25L12835F,%203V,%20128Mb,%20v1.6.pdf)
+- [flashrom](https://flashrom.org/Flashrom)