diff options
| author | Martin Roth <martin@coreboot.org> | 2021-10-01 14:10:19 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2021-10-05 18:06:24 +0000 |
| commit | 6c3ece9c9ef73db5c0e02cc5a41c98f46b86c3e9 (patch) | |
| tree | 23a804c556938f20002a2727ac62495a9bb982fe /Documentation/northbridge | |
| parent | d4c55353e044e157994eaf15b78103a9473e5440 (diff) | |
| download | coreboot-6c3ece9c9ef73db5c0e02cc5a41c98f46b86c3e9.tar.gz coreboot-6c3ece9c9ef73db5c0e02cc5a41c98f46b86c3e9.tar.bz2 coreboot-6c3ece9c9ef73db5c0e02cc5a41c98f46b86c3e9.zip | |
Documentation: Fix spelling errors
These issues were found and fixed by codespell, a useful tool for
finding spelling errors.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: If2a8e97911420c19e9365d5c28810b998f2c2ac8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58078
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'Documentation/northbridge')
3 files changed, 4 insertions, 4 deletions
diff --git a/Documentation/northbridge/intel/sandybridge/nri.md b/Documentation/northbridge/intel/sandybridge/nri.md index bf0b89f6a09a..1cd5fb40149b 100644 --- a/Documentation/northbridge/intel/sandybridge/nri.md +++ b/Documentation/northbridge/intel/sandybridge/nri.md @@ -40,7 +40,7 @@ The memory initialization code has to take care of lots of duties: +---------+-------------------------------------------------------------------+------------+--------------+ ``` -## (Unoffical) register documentation +## (Unofficial) register documentation - [Sandy Bridge - Register documentation](nri_registers.md) ## Frequency selection @@ -101,7 +101,7 @@ is stored to MRC cache. As of writing the only supported error handling is to disable the failing channel and restart the memory training sequence. It's very likely to succeed, as memory channels operate independent of each other. -In case no DIMM could be initilized coreboot will halt. The screen will stay +In case no DIMM could be initialized coreboot will halt. The screen will stay black until you power of your device. On some platforms there's additional feedback to indicate such an event. diff --git a/Documentation/northbridge/intel/sandybridge/nri_freq.md b/Documentation/northbridge/intel/sandybridge/nri_freq.md index 208c1cb13c48..8d66b5c234d2 100644 --- a/Documentation/northbridge/intel/sandybridge/nri_freq.md +++ b/Documentation/northbridge/intel/sandybridge/nri_freq.md @@ -42,7 +42,7 @@ Only **XMP profile 1** is being used in case it advertises: * 1.5V operating voltage * The channel's installed DIMM count doesn't exceed the XMP coded limit -In case the XMP profile doesn't fullfill those limits, the regular SPD will be +In case the XMP profile doesn't fulfill those limits, the regular SPD will be used. > **Note:** XMP Profiles are supported since coreboot 4.4. diff --git a/Documentation/northbridge/intel/sandybridge/nri_registers.md b/Documentation/northbridge/intel/sandybridge/nri_registers.md index aae1205ec6e9..32bd3d1e2867 100644 --- a/Documentation/northbridge/intel/sandybridge/nri_registers.md +++ b/Documentation/northbridge/intel/sandybridge/nri_registers.md @@ -1947,7 +1947,7 @@ Please handle with care! +-----------+------------------------------------------------------------------+ | Bit | Description | +===========+==================================================================+ -| 0:7| OREF_RI, Rank idle period that defines an oppertunity for | +| 0:7| OREF_RI, Rank idle period that defines an opportunity for | | | refresh | +-----------+------------------------------------------------------------------+ | 8:11| Refresh_HP_WM, tREFI count level that turns the refresh | |