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| author | Angel Pons <th3fanbus@gmail.com> | 2021-05-10 23:30:45 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-05-12 08:01:00 +0000 |
| commit | 918e5352b747fe08158f0bc06975342024e385f0 (patch) | |
| tree | 88251ddae0c9ed2d256720414e9b1188017a30fc /Documentation/northbridge | |
| parent | 23e15b1223b3a608f04851c62bd1a87e0cc9e68d (diff) | |
| download | coreboot-918e5352b747fe08158f0bc06975342024e385f0.tar.gz coreboot-918e5352b747fe08158f0bc06975342024e385f0.tar.bz2 coreboot-918e5352b747fe08158f0bc06975342024e385f0.zip | |
Doc/nb/intel/sandybridge: Fix up some typos and cosmetics
Change-Id: I23b0c94ec9881aef8e39a14bc048856a65a6286d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'Documentation/northbridge')
| -rw-r--r-- | Documentation/northbridge/intel/sandybridge/index.md | 2 | ||||
| -rw-r--r-- | Documentation/northbridge/intel/sandybridge/nri.md | 4 | ||||
| -rw-r--r-- | Documentation/northbridge/intel/sandybridge/nri_registers.md | 4 |
3 files changed, 5 insertions, 5 deletions
diff --git a/Documentation/northbridge/intel/sandybridge/index.md b/Documentation/northbridge/intel/sandybridge/index.md index c1d4b9948d2a..27fbb2cc2ebe 100644 --- a/Documentation/northbridge/intel/sandybridge/index.md +++ b/Documentation/northbridge/intel/sandybridge/index.md @@ -4,6 +4,6 @@ This section contains documentation about coreboot on specific Intel "Sandy Brid ## Topics -- [Native Ram Initialization](nri.md) +- [Native RAM Initialization](nri.md) - [RAM initialization feature matrix](nri_features.md) - [ME Cleaner](me_cleaner.md) diff --git a/Documentation/northbridge/intel/sandybridge/nri.md b/Documentation/northbridge/intel/sandybridge/nri.md index 812cd23fdb67..bf0b89f6a09a 100644 --- a/Documentation/northbridge/intel/sandybridge/nri.md +++ b/Documentation/northbridge/intel/sandybridge/nri.md @@ -40,7 +40,7 @@ The memory initialization code has to take care of lots of duties: +---------+-------------------------------------------------------------------+------------+--------------+ ``` -## (Inoffical) register documentation +## (Unoffical) register documentation - [Sandy Bridge - Register documentation](nri_registers.md) ## Frequency selection @@ -83,7 +83,7 @@ in each DIMM's SPD. > **Note:** This feature is available since coreboot 4.4 ### MRC cache -The name *MRC cache* might be missleading as in case of *Native ram init* +The name *MRC cache* might be misleading as in case of *Native RAM init* there's no MRC, but for historical reasons it's still named *MRC cache*. The MRC cache is part of flash memory that is writeable by coreboot. At the end of the boot process coreboot will write the RAM training results to diff --git a/Documentation/northbridge/intel/sandybridge/nri_registers.md b/Documentation/northbridge/intel/sandybridge/nri_registers.md index 8f85629061ea..aae1205ec6e9 100644 --- a/Documentation/northbridge/intel/sandybridge/nri_registers.md +++ b/Documentation/northbridge/intel/sandybridge/nri_registers.md @@ -1,9 +1,9 @@ -# Inoffical Documentation of Intel MCHBAR register space. +# Unofficial Documentation of Intel MCHBAR register space. The MCHBAR can be enabled by using register 0x48 of PCI(0:0:0) device. This documentation is incomplete and might be incorrect. -Please handle with care ! +Please handle with care! **MCHBAR + 0x4** |