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| author | Miriam Polzer <mpolzer@google.com> | 2021-11-10 12:45:28 +0100 |
|---|---|---|
| committer | Julius Werner <jwerner@chromium.org> | 2021-11-19 17:19:50 +0000 |
| commit | 7dce19080889955576f8fd197658077aced96a96 (patch) | |
| tree | 5a5d77ed9239cc7e1504d9d9293203770b2cffda /Documentation/soc/intel | |
| parent | bef23d1f79bffbec472e1ea832eac4902c5a3d8a (diff) | |
| download | coreboot-7dce19080889955576f8fd197658077aced96a96.tar.gz coreboot-7dce19080889955576f8fd197658077aced96a96.tar.bz2 coreboot-7dce19080889955576f8fd197658077aced96a96.zip | |
security/vboot: Add NVRAM counter for TPM 2.0
Create an NVRAM counter in TPM 2.0 that survives owner clear and can be
read and written without authorization. This counter allows to seal data
with the TPM that can only be unsealed before the counter was
incremented. It will be used during Chrome OS rollback to securely carry
data across a TPM clear.
Signed-off-by: Miriam Polzer <mpolzer@google.com>
Change-Id: I511dba3b3461713ce20fb2bda9fced0fee6517e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'Documentation/soc/intel')
0 files changed, 0 insertions, 0 deletions