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| author | Raul E Rangel <rrangel@chromium.org> | 2020-05-13 14:01:09 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-18 07:40:51 +0000 |
| commit | cbaa835f211eb04ba6eb5e9c3c0095534e93a100 (patch) | |
| tree | e7adc4100c429d0fb4daeb91497f9e073db37293 /Documentation/soc | |
| parent | f836a234e211266d1feffd5f406a692ac0fba164 (diff) | |
| download | coreboot-cbaa835f211eb04ba6eb5e9c3c0095534e93a100.tar.gz coreboot-cbaa835f211eb04ba6eb5e9c3c0095534e93a100.tar.bz2 coreboot-cbaa835f211eb04ba6eb5e9c3c0095534e93a100.zip | |
soc/amd/picasso/Makefile: Use apcb_tool to generate APCBs from SPDs
BUG=b:147042464
TEST=Boot trembyle to OS
Signed-off-by: Rob Barnes <robbarnes@google.com>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ife48d5268230f70c6a6f4a56c1f0d05b6c924891
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41381
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'Documentation/soc')
| -rwxr-xr-x | Documentation/soc/amd/family17h.md | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/Documentation/soc/amd/family17h.md b/Documentation/soc/amd/family17h.md index b917c94526c7..23088cd12bab 100755 --- a/Documentation/soc/amd/family17h.md +++ b/Documentation/soc/amd/family17h.md @@ -237,6 +237,51 @@ Picasso's FSP is compatible with rev. 2.0 of the External Architecture Specification. Deviations, e.g., no FSP-T support, shall be published in an Integration Guide. +## APCB setup + +APCBs are used to provide the PSP with SPD information and optionally a set of +GPIOs to use for selecting which SPD to load. + +### Prebuilt +The picasso `Makefile` expects APCBs to be located in +`3rdparty/blobs/mainboard/$(MAINBOARDDIR)`. If you have a pre-built binary just +add the following to your mainboard's Makefile. + +``` +# i.e., 3rdparty/blobs/mainboard/amd/mandolin/APCB_mandolin.bin +APCB_SOURCES = mandolin +``` + +### Generating APCBs +If you have a template APCB file, the `apcb_edit` tool can be used to inject the +SPD and GPIOs used to select the correct slot. Entries should match this +pattern `{NAME}_x{1,2}`. There should be a matching SPD hex file in +`SPD_SOURCES_DIR` matching the pattern `{NAME}.spd.hex`. +The `_x{1,2}` suffix denotes single or dual channel. Up to 16 slots can be used. +If a slot is empty, the special empty keyword can be used. This will generate +an APCB with an empty SPD. + +``` +APCB_SOURCES = hynix-HMA851S6CJR6N-VK_x1 # 0b0000 +APCB_SOURCES += hynix-HMAA1GS6CMR6N-VK_x2 # 0b0001 +APCB_SOURCES += empty # 0b0010 +APCB_SOURCES += samsung-K4A8G165WC-BCWE_x1 # 0b0011 +``` + +#### APCB Board ID GPIO configuration. +The GPIOs determine which memory SPD will be used during boot. +``` +# APCB_BOARD_ID_GPIO[0-3] = GPIO_NUMBER GPIO_IO_MUX GPIO_BANK_CTL +# GPIO_NUMBER: FCH GPIO number +# GPIO_IO_MUX: Value write to IOMUX to configure this GPIO +# GPIO_BANK_CTL: Value write to GPIOBankCtl[23:16] to configure this GPIO + +APCB_BOARD_ID_GPIO0 = 121 1 0 +APCB_BOARD_ID_GPIO1 = 120 1 0 +APCB_BOARD_ID_GPIO2 = 131 3 0 +APCB_BOARD_ID_GPIO3 = 116 1 0 +``` + ## Footnotes 1. *AMD Platform Security Processor BIOS Architecture Design Guide |