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authorAndrey Petrov <anpetrov@fb.com>2019-10-11 11:31:08 -0700
committerPatrick Georgi <pgeorgi@google.com>2019-10-16 14:11:17 +0000
commitee0b7ad683fabafef228c624348057d31fe1e6d2 (patch)
treed7f29474b13e94f3e3f2a1745749a5725fed80f9 /Documentation/soc
parent89f596764775f5de53d4e17a95d2ec88c254e24a (diff)
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mainboard/ocp/monolake: Hide IIO root ports before memory init
It turned on some SKUs FSP hangs in Notify stage if IIO root ports are disabled after MemoryInit. To address that hide IIO root ports earlier in romstage. TEST=the patch was ran on affected HW and success was reported Change-Id: I6a2a405f729df14f46bcf34a24e66e8ba9415f9d Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'Documentation/soc')
-rw-r--r--Documentation/soc/intel/fsp/index.md7
1 files changed, 7 insertions, 0 deletions
diff --git a/Documentation/soc/intel/fsp/index.md b/Documentation/soc/intel/fsp/index.md
index cd7fe0b30203..aac7b35a50c6 100644
--- a/Documentation/soc/intel/fsp/index.md
+++ b/Documentation/soc/intel/fsp/index.md
@@ -21,6 +21,12 @@ those are fixed. If possible a workaround is described here as well.
* Workaround: Don't disable this PCI device
* Issue on public tracker: [Issue 13]
+* FSP Notify(EnumInitPhaseAfterPciEnumeration) hangs if 00:02.03/00:02.03 are hidden
+ * Release MR2
+ * Seems to get stuck on some SKUs only if hidden after MemoryInit
+ * Workaround: Hide before MemoryInit
+ * Issue on public tracker: [Issue 35]
+
### KabylakeFsp
* MfgId and ModulePartNum in the DIMM_INFO struct are empty
* Release 3.7.1
@@ -59,4 +65,5 @@ those are fixed. If possible a workaround is described here as well.
[Issue 13]: https://github.com/IntelFsp/FSP/issues/13
[Issue 15]: https://github.com/IntelFsp/FSP/issues/15
[Issue 22]: https://github.com/IntelFsp/FSP/issues/22
+[Issue 35]: https://github.com/IntelFsp/FSP/issues/35