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| author | Angel Pons <th3fanbus@gmail.com> | 2021-11-14 15:34:02 +0100 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2021-11-19 13:54:48 +0000 |
| commit | 65adc701652e4ad9e9cf26d82dcc7eaeae52d898 (patch) | |
| tree | 50edcdee93b023832a0abc1f4ad7c949a8707e1c /Documentation/superio | |
| parent | c9bc7a7591d9b667e4249b98e4037d6e7239f2e8 (diff) | |
| download | coreboot-65adc701652e4ad9e9cf26d82dcc7eaeae52d898.tar.gz coreboot-65adc701652e4ad9e9cf26d82dcc7eaeae52d898.tar.bz2 coreboot-65adc701652e4ad9e9cf26d82dcc7eaeae52d898.zip | |
util/inteltool: Add ICH10D PCI ID
Add the PCI device ID for the ICH10D southbridge. While we're at it,
also fix up whitespace in inteltool.h of an adjacent definition.
Change-Id: I98d88a9ce27d3ddaafd7123ee51b2111a8bef019
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Diffstat (limited to 'Documentation/superio')
0 files changed, 0 insertions, 0 deletions