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| author | Karthikeyan Ramasubramanian <kramasub@google.com> | 2021-08-31 12:39:47 -0600 |
|---|---|---|
| committer | Karthik Ramasubramanian <kramasub@google.com> | 2021-09-01 19:36:20 +0000 |
| commit | c2310a16adaca7ac32f21c083258ceb27d12ab89 (patch) | |
| tree | f8db7478ccecea0ccd01e13e0866756af9dca3c8 /Documentation/tutorial/part3.md | |
| parent | c35659d930d038da714c22d1a8157c67aa9ae69f (diff) | |
| download | coreboot-c2310a16adaca7ac32f21c083258ceb27d12ab89.tar.gz coreboot-c2310a16adaca7ac32f21c083258ceb27d12ab89.tar.bz2 coreboot-c2310a16adaca7ac32f21c083258ceb27d12ab89.zip | |
soc/amd/cezanne: Increase the FSP_M_SIZE configuration
On mainboards with Cezanne SOC, serial enabled FSP_M binary size is
greater than the size allocated in DRAM. Increase the allocated size for
FSP_M binary in DRAM to handle both debug and release FSP_M binaries.
Also adjust the verstage load address accordingly.
BUG=None
TEST=Build and boot to OS in guybrush with both debug and release FSP_M.
Perform warm, cold reboot and suspend/resume cycling for 10 iterations.
Change-Id: Ic6f90041e258039e691cbdb3a978cfe1f782642a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57293
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'Documentation/tutorial/part3.md')
0 files changed, 0 insertions, 0 deletions