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| author | Rob Barnes <robbarnes@google.com> | 2021-12-21 07:19:12 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-10 14:25:32 +0000 |
| commit | f26ce9f00e79a73631ec631ae89a5763284a3bb3 (patch) | |
| tree | 4b295fbc155740c3b6490dae661ffec9717b4458 /Documentation/util.md | |
| parent | d2bba5ccd818417ad146914c95899989ff663e8e (diff) | |
| download | coreboot-f26ce9f00e79a73631ec631ae89a5763284a3bb3.tar.gz coreboot-f26ce9f00e79a73631ec631ae89a5763284a3bb3.tar.bz2 coreboot-f26ce9f00e79a73631ec631ae89a5763284a3bb3.zip | |
util/apcb: Add apcb_v3_edit tool
apcb_v3_edit.py tool edits APCB V3 binaries. Specifically it will inject
up to 16 SPDs into an existing APCB. The APCB must have a magic number
at the top of each SPD slot.
BUG=b:209486191
BRANCH=None
TEST=Inject 4 SPDs into magic APCB, boot guybrush with modified APCB
Change-Id: I9148977c415df41210a3a13a1cd9b3bc1504a480
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'Documentation/util.md')
| -rw-r--r-- | Documentation/util.md | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/Documentation/util.md b/Documentation/util.md index 8c6bcb7fcad8..b618dccc4482 100644 --- a/Documentation/util.md +++ b/Documentation/util.md @@ -12,6 +12,8 @@ settings. `Perl` * __apcb__ - AMD PSP Control Block tools * _apcb_edit.py_ - This tool allows patching an existing APCB binary with specific SPDs and GPIO selection pins. `Python3` + * _apcb_v3_edit.py_ - This tool allows patching an existing APCB V3 +binary with specific SPDs. `Python3` * __archive__ - Concatenate files and create an archive `C` * __autoport__ - Automated porting coreboot to Sandy Bridge/Ivy Bridge platforms `Go` |