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| author | Lijian Zhao <lijian.zhao@intel.com> | 2018-11-29 16:24:24 -0800 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2018-12-04 23:29:28 +0000 |
| commit | ad1e49afacae6e38cc7d735f67b6f2afb6d9fb71 (patch) | |
| tree | 25538b52b5e4dfe3eff86bc9fea44b7fa7a08467 /Documentation | |
| parent | 46f3fa825fa8f1ca93bfcb814e18e997a082443b (diff) | |
| download | coreboot-ad1e49afacae6e38cc7d735f67b6f2afb6d9fb71.tar.gz coreboot-ad1e49afacae6e38cc7d735f67b6f2afb6d9fb71.tar.bz2 coreboot-ad1e49afacae6e38cc7d735f67b6f2afb6d9fb71.zip | |
soc/intel/common: Limit BIOS region cache to 16MB
Cache BIOS region can boost boot performance, however it can't be over
16MB, according to processor EDS vol1(Apollolake/Skylake/WhiskeyLake),
FLASH+APIC LT will be less than 20MB under 4G. Set the maxiam to 16GB
to save numbers of mtrr entries.
BUG=b:119267832
TEST=Build and boot up fine on whiskeylake rvp platform.
Change-Id: I46a47c8bf66b14fb2fcb7b6b1d30d02886c450a4
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/29944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'Documentation')
0 files changed, 0 insertions, 0 deletions