mb/foxconn/d41s: Add mainboard

This supports the Foxconn d41s, d42s, d51s, d52s.

The following is tested (SeaBIOS 1.12 + Linux 4.9) and works:
- COM1
- S3 resume (with SeaBIOS needs sercon disabled)
- Native graphic init on VGA output
- SATA
- USB
- Ethernet
- PS2 keyboard

The base for this mainboard port was the Intel D510MO port.

Change-Id: Ie4ec9cbf70adcdddbc2e5d805e4806825c320072
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28227
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

3 files changed, 79 insertions, 0 deletions

diff --git a/Documentation/mainboard/foxconn/d41s.md b/Documentation/mainboard/foxconn/d41s.md
new file mode 100644
index 000000000000..fe14057d3452
--- /dev/null
+++ b/Documentation/mainboard/foxconn/d41s.md
@@ -0,0 +1,75 @@
+# Foxconn D41S
+
+This page describes how to run coreboot on the [FOXCONN D41S] desktop from [FOXCONN].
+The D42S, D51S, D52S are compatible boards with the difference being the CPU.
+
+## Building coreboot
+
+The default options for this board should result in a fully working image:
+
+	# echo "CONFIG_VENDOR_FOXCONN=y" > .config
+	# echo "CONFIG_BOARD_FOXCONN_D41S=y" >> .config
+	# make olddefconfig && make
+
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+--------+
+| Type                | Value  |
++=====================+========+
+| Socketed flash      | yes    |
++---------------------+--------+
+| Model               | W25X80 |
++---------------------+--------+
+| Size                | 1 MiB  |
++---------------------+--------+
+| In circuit flashing | yes    |
++---------------------+--------+
+| Package             | DIP-8  |
++---------------------+--------+
+| Write protection    | No     |
++---------------------+--------+
+| Dual BIOS feature   | No     |
++---------------------+--------+
+| Internal flashing   | yes    |
++---------------------+--------+
+```
+
+### Internal programming
+
+The SPI flash can be accessed using [flashrom].
+
+### External programming
+
+The easiest to flash externally is to simply extract the SPI flash from its socket.
+To do this gently take the SPI flash out of its socket and flash with your programmer.
+
+**NOTE: Don't forget to set the WP# AND HOLD# to 3V.**
+
+**NOTE2: Make sure to reinsert it in the right direction afterward**
+
+**Location and orientation of the SPI flash socket**
+![][d41s_flash]
+
+[d41s_flash]: d41s_flash.jpg
+
+## Technology
+
+```eval_rst
++------------------+------------------+
+| Northbridge      | Intel Pinevew    |
++------------------+------------------+
+| Southbridge      | Intel NM10       |
++------------------+------------------+
+| CPU              | model_106cx      |
++------------------+------------------+
+| SuperIO          | ITE IT8721F      |
++------------------+------------------+
+| clockgen (CK505) | ICS 9LPRS525AGLF |
++------------------+------------------+
+```
+
+[FOXCONN D41S]: http://www.foxconnchannel.com/ProductDetail.aspx?T=motherboard&U=en-us0000481
+[FOXCONN]: http://www.foxconnchannel.com
+[Flashrom]: https://flashrom.org/Flashrom
diff --git a/Documentation/mainboard/foxconn/d41s_flash.jpg b/Documentation/mainboard/foxconn/d41s_flash.jpg
new file mode 100644
index 000000000000..79f3b32e9c56
--- /dev/null
+++ b/Documentation/mainboard/foxconn/d41s_flash.jpg
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index 8bf0963a6d02..6c75ea28c638 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -10,6 +10,10 @@ This section contains documentation about coreboot on specific mainboards.
 
 - [CN81XX EVB SFF](cavium/cn8100_sff_evb.md)
 
+## Foxconn
+
+- [D41S](foxconn/d41s.md)
+
 ## Gigabyte
 
 - [GA-H61M-S2PV](gigabyte/ga-h61m-s2pv.md)