diff options
| author | Werner Zeh <werner.zeh@siemens.com> | 2021-07-20 14:07:02 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-07-22 09:40:57 +0000 |
| commit | 8dd1a54f0922a8cc600c8fc943dcb4ed5516803b (patch) | |
| tree | 91156ccef0d5a733e662db30a4f455e906acf1eb /Makefile.inc | |
| parent | 3ee18cefa3e8a33720e9f62c4034f9fa76789105 (diff) | |
| download | coreboot-8dd1a54f0922a8cc600c8fc943dcb4ed5516803b.tar.gz coreboot-8dd1a54f0922a8cc600c8fc943dcb4ed5516803b.tar.bz2 coreboot-8dd1a54f0922a8cc600c8fc943dcb4ed5516803b.zip | |
mb/siemens/mc_ehl1: Adjust PCIe settings in devicetree
This board does not use CLKREQ-signaling for PCIe, so disable the pin
assignments. In addition only three clock outputs are used for PCIe,
therefore disable all others to improve EMI.
Change-Id: I545f890fa55a109df7f44d2c82170874fb769009
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56455
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'Makefile.inc')
0 files changed, 0 insertions, 0 deletions