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| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2022-10-29 21:32:54 +0200 |
|---|---|---|
| committer | Michał Żygowski <michal.zygowski@3mdeb.com> | 2023-06-23 08:59:50 +0000 |
| commit | 95be012c11936676f6573880d5fd01826ae6f9fe (patch) | |
| tree | 6ca992dc8602b24a402d4c6c2d40f5d6ee152281 /Makefile.inc | |
| parent | 558d8b79e6b898e0f63772993f578aa4dd42128b (diff) | |
| download | coreboot-95be012c11936676f6573880d5fd01826ae6f9fe.tar.gz coreboot-95be012c11936676f6573880d5fd01826ae6f9fe.tar.bz2 coreboot-95be012c11936676f6573880d5fd01826ae6f9fe.zip | |
soc/intel/alderlake/hsphy: Add possibility to cache HSPHY in flash
The patch adds a possibility to cache the PCIe 5.0 HSPHY firmware in
the SPI flash. New flashmap region is created for that purpose. The
goal of caching is to reduce the dependency on CSME and the HECI IP
LOAD command which may fail when the CSME is disabled, e.g. soft
disabled by HECI command or HAP disabled. This change allows to
keep PCIe 5.0 root ports functioning even if CSME/HECI is not
functional.
TEST=Boot Ubuntu 22.04 on MSI PRO Z690-A and notice PCIe 5.0 port
is functional after loading the HSPHY from cache.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I5a37f5b06706ff30d92f60f1bf5dc900edbde96f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68987
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'Makefile.inc')
| -rw-r--r-- | Makefile.inc | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/Makefile.inc b/Makefile.inc index b35ec86a1100..ab57abd4ceb7 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -1029,6 +1029,15 @@ else FMAP_VPD_ENTRY := endif +ifeq ($(CONFIG_INCLUDE_HSPHY_IN_FMAP),y) +FMAP_HSPHY_FW_BASE := $(call int-align, $(FMAP_CURRENT_BASE), 0x1000) +FMAP_HSPHY_FW_SIZE := $(CONFIG_HSPHY_FW_MAX_SIZE) +FMAP_HSPHY_FW_ENTRY := HSPHY_FW@$(FMAP_HSPHY_FW_BASE) $(FMAP_HSPHY_FW_SIZE) +FMAP_CURRENT_BASE := $(call int-add, $(FMAP_HSPHY_FW_BASE) $(FMAP_HSPHY_FW_SIZE)) +else +FMAP_HSPHY_FW_ENTRY := +endif + # # X86 FMAP region # @@ -1107,6 +1116,7 @@ $(obj)/fmap.fmd: $(top)/Makefile.inc $(DEFAULT_FLASHMAP) $(obj)/config.h -e "s,##SMMSTORE_ENTRY##,$(FMAP_SMMSTORE_ENTRY)," \ -e "s,##SPD_CACHE_ENTRY##,$(FMAP_SPD_CACHE_ENTRY)," \ -e "s,##VPD_ENTRY##,$(FMAP_VPD_ENTRY)," \ + -e "s,##HSPHY_FW_ENTRY##,$(FMAP_HSPHY_FW_ENTRY)," \ -e "s,##CBFS_BASE##,$(FMAP_CBFS_BASE)," \ -e "s,##CBFS_SIZE##,$(FMAP_CBFS_SIZE)," \ $(DEFAULT_FLASHMAP) > $@.tmp |