Add a first bit of a framework. Builds the following parts, in

accordance to the newboot document:

* reset vector (16 bytes)
* vpd (240bytes)
* boot block (8k - 256b)
* lar archive (256-8 k)

The boot block is kind of simple, still. It enables pmode, car, and
starts looking for an initram module in the lar archive.

Note: This doesnt do much at the moment,
as gas seems to produce buggy code in init.S.

Take this as a suggestion of how it might work and please provide
patches fixing it and bringing it into shape.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@62 f3766cd6-281f-0410-b1cd-43a5c92072e9

2 files changed, 154 insertions, 0 deletions

diff --git a/lib/lar.c b/lib/lar.c
new file mode 100644
index 000000000000..0b8c26803d5d
--- /dev/null
+++ b/lib/lar.c
@@ -0,0 +1,63 @@
+/*
+ * lar - LinuxBIOS archiver
+ *
+ * Copright (C) 2006-2007 coresystems GmbH
+ * Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ *
+ */
+
+#include <arch/types.h>
+#include <string.h>
+#include <lar.h>
+
+#ifndef CONFIG_BIG_ENDIAN
+#define ntohl(x) ( ((x&0xff)<<24) | ((x&0xff00)<<8) | \
+		((x&0xff0000) >> 8) | ((x&0xff000000) >> 24) )
+#else
+#define ntohl(x) (x)
+#endif
+
+int find_file(struct mem_file *archive, char *filename, struct mem_file *result)
+{
+	char * walk, *fullname;
+	struct lar_header * header;
+	
+	for (walk = archive->start; walk < (char *)archive->start + 
+			archive->len; walk+=16) {
+
+		if(strcmp(walk, MAGIC)!=0)
+			continue;
+
+		header=(struct lar_header *)walk;
+		fullname=walk+sizeof(struct lar_header);
+
+		// FIXME: check checksum
+		
+		if(strcmp(fullname, filename)!=0) {
+			result->start=walk + ntohl(header->offset);
+			result->len=ntohl(header->len);
+			return 0;
+		}
+
+		// skip file
+		walk += ( ntohl(header->offset) + ntohl(header->len)
+				+ 15 ) & 0xfffffff0;
+	}
+
+	return 1;
+}
+
+
diff --git a/lib/uart8250.c b/lib/uart8250.c
new file mode 100644
index 000000000000..9eca833be298
--- /dev/null
+++ b/lib/uart8250.c
@@ -0,0 +1,91 @@
+/* Should support 8250, 16450, 16550, 16550A type uarts */
+#include <arch/io.h>
+#include <uart8250.h>
+#include "../arch/x86/config.h" // for ttyS0 base FIXME!
+
+/* Data */
+#define UART_RBR 0x00
+#define UART_TBR 0x00
+
+/* Control */
+#define UART_IER 0x01
+#define UART_IIR 0x02
+#define UART_FCR 0x02
+#define UART_LCR 0x03
+#define UART_MCR 0x04
+#define UART_DLL 0x00
+#define UART_DLM 0x01
+
+/* Status */
+#define UART_LSR 0x05
+#define UART_MSR 0x06
+#define UART_SCR 0x07
+
+static inline int uart8250_can_tx_byte(unsigned base_port)
+{
+	return inb(base_port + UART_LSR) & 0x20;
+}
+
+static inline void uart8250_wait_to_tx_byte(unsigned base_port)
+{
+	while(!uart8250_can_tx_byte(base_port))
+		;
+}
+
+static inline void uart8250_wait_until_sent(unsigned base_port)
+{
+	while(!(inb(base_port + UART_LSR) & 0x40)) 
+		;
+}
+
+void uart8250_tx_byte(unsigned base_port, unsigned char data)
+{
+	uart8250_wait_to_tx_byte(base_port);
+	outb(data, base_port + UART_TBR);
+	/* Make certain the data clears the fifos */
+	uart8250_wait_until_sent(base_port);
+}
+
+int uart8250_can_rx_byte(unsigned base_port)
+{
+	return inb(base_port + UART_LSR) & 0x01;
+}
+
+unsigned char uart8250_rx_byte(unsigned base_port)
+{
+	while(!uart8250_can_rx_byte(base_port))
+		;
+	return inb(base_port + UART_RBR);
+}
+
+void uart8250_init(unsigned base_port, unsigned divisor, unsigned lcs)
+{
+	lcs &= 0x7f;
+	/* disable interrupts */
+	outb(0x0, base_port + UART_IER);
+	/* enable fifo's */
+	outb(0x01, base_port + UART_FCR);
+	/* assert DTR and RTS so the other end is happy */
+	outb(0x03, base_port + UART_MCR);
+	/* Set Baud Rate Divisor to 12 ==> 115200 Baud */
+	outb(0x80 | lcs, base_port + UART_LCR);
+	outb(divisor & 0xFF,   base_port + UART_DLL);
+	outb((divisor >> 8) & 0xFF,    base_port + UART_DLM);
+	outb(lcs, base_port + UART_LCR);
+}
+
+/* Initialize a generic uart */
+void init_uart8250(unsigned base_port, struct uart8250 *uart)
+{
+	int divisor;
+	int lcs;
+	divisor = 115200/(uart->baud ? uart->baud: 1);
+	lcs = 3;
+	if (base_port == TTYS0_BASE) {
+		/* Don't reinitialize the console serial port,
+		 * This is espeically nasty in SMP.
+		 */
+		return;
+	}
+	uart8250_init(base_port, divisor, lcs);
+}