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| author | Ivy Jian <ivy.jian@quanta.corp-partner.google.com> | 2023-11-28 15:17:40 +0800 |
|---|---|---|
| committer | Shelley Chen <shchen@google.com> | 2023-12-01 00:12:27 +0000 |
| commit | 1397fd3668c73b940253e5f5a5f81dea54383660 (patch) | |
| tree | 223ee5c1d60aba6ab36628d5154c01f68318b58b /payloads/libpayload/arch/x86/head.S | |
| parent | 2873cc68043adecefd4640718f6b94dad0f0ae3f (diff) | |
| download | coreboot-1397fd3668c73b940253e5f5a5f81dea54383660.tar.gz coreboot-1397fd3668c73b940253e5f5a5f81dea54383660.tar.bz2 coreboot-1397fd3668c73b940253e5f5a5f81dea54383660.zip | |
mb/google/brox: Update storage settings for SSD and UFS
Brox has SSD and UFS storage per different SKU.
1. Set SSD on CPU PCIe port (PCIEX4_A) and configure related gpio
settings according to the schematic.
2. Enable UFS, also enable ISH since it is PCI function 0, required
for UFS function 7 to be enabled.
3. Set unused SRCCLKREQ signals to NC.
4. Remove unused gpio settings in variant gpio table to prevent
unexpected overrides.
BUG=b:311450057
BRANCH=None
TEST=emerge-brox coreboot
Change-Id: I88922bcfa13652006aa10078c3c444624fd4575e
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79295
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'payloads/libpayload/arch/x86/head.S')
0 files changed, 0 insertions, 0 deletions