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| author | Jianjun Wang <jianjun.wang@mediatek.com> | 2021-07-28 16:53:43 +0800 |
|---|---|---|
| committer | Yu-Ping Wu <yupingso@google.com> | 2022-05-20 02:53:35 +0000 |
| commit | 20a87c0bed98fe8817a2dfccf4cd271199aabc1a (patch) | |
| tree | fc9deb0205c596fbd8c448f24f9fca74a1fa8bfa /payloads/libpayload/drivers/pcie_mediatek.c | |
| parent | 2ad74deb2a11772cdd23c3613b58e9116b36863a (diff) | |
| download | coreboot-20a87c0bed98fe8817a2dfccf4cd271199aabc1a.tar.gz coreboot-20a87c0bed98fe8817a2dfccf4cd271199aabc1a.tar.bz2 coreboot-20a87c0bed98fe8817a2dfccf4cd271199aabc1a.zip | |
libpayload/pci: Add pci_map_bus function for MediaTek platform
Add 'pci_map_bus' function and PCIE_MEDIATEK config for MediaTek
platform.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
BRANCH=cherry
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: I9ea7d111fed6b816fa2352fe93c268116519a577
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'payloads/libpayload/drivers/pcie_mediatek.c')
| -rw-r--r-- | payloads/libpayload/drivers/pcie_mediatek.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/payloads/libpayload/drivers/pcie_mediatek.c b/payloads/libpayload/drivers/pcie_mediatek.c new file mode 100644 index 000000000000..a953bd7fae6c --- /dev/null +++ b/payloads/libpayload/drivers/pcie_mediatek.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <libpayload.h> +#include <pci.h> + +#define PCIE_CFGNUM_REG 0x140 +#define PCIE_CFG_DEVFN(devfn) ((devfn) & GENMASK(7, 0)) +#define PCIE_CFG_BUS(bus) (((bus) << 8) & GENMASK(15, 8)) +#define PCIE_CFG_OFFSET_ADDR 0x1000 +#define PCIE_CFG_HEADER(bus, devfn) \ + (PCIE_CFG_BUS(bus) | PCIE_CFG_DEVFN(devfn)) + +uintptr_t pci_map_bus(pcidev_t dev) +{ + u32 devfn = (PCI_SLOT(dev) << 3) | PCI_FUNC(dev); + u32 val = PCIE_CFG_HEADER(PCI_BUS(dev), devfn); + write32((void *)(lib_sysinfo.pcie_ctrl_base + PCIE_CFGNUM_REG), val); + + return lib_sysinfo.pcie_ctrl_base + PCIE_CFG_OFFSET_ADDR; +} |