libpayload/pci: Add support for bus mapping

Move the common APIs to pci_ops.c and IO based operations to
pci_io_ops.c, and add pci_map_bus_ops.c to support bus mapping.

TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
 == NVME IDENTIFY CONTROLLER DATA ==
    PCI VID   : 0x15b7
    PCI SSVID : 0x15b7
    SN        : 21517J440114
    MN        : WDC PC SN530 SDBPTPZ-256G-1006
    RAB       : 0x4
    AERL      : 0x7
    SQES      : 0x66
    CQES      : 0x44
    NN        : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006

BUG=b:178565024
BRANCH=cherry

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Ie74801bd4f3de51cbb574e86cd9bb09931152554
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>

6 files changed, 138 insertions, 45 deletions

diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig
index 4f8896aa6e28..7540c674a2c9 100644
--- a/payloads/libpayload/Kconfig
+++ b/payloads/libpayload/Kconfig
@@ -404,8 +404,14 @@ menu "Drivers"
 
 config PCI
 	bool "Support for PCI devices"
-	depends on ARCH_X86 # for now
-	default y
+	default y if ARCH_X86
+	default n
+
+config PCI_IO_OPS
+	bool "Support for PCI devices with port IO"
+	depends on PCI && IO_ADDRESS_SPACE
+	default y if ARCH_X86
+	default n
 
 config NVRAM
 	bool "Support for reading/writing NVRAM bytes"
diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc
index 41fda5be1e15..b2a91f6610f8 100644
--- a/payloads/libpayload/drivers/Makefile.inc
+++ b/payloads/libpayload/drivers/Makefile.inc
@@ -28,7 +28,13 @@
 ## SUCH DAMAGE.
 ##
 
-libc-$(CONFIG_LP_PCI) += pci.c
+libc-$(CONFIG_LP_PCI) += pci_ops.c
+
+ifeq ($(CONFIG_LP_PCI_IO_OPS),y)
+libc-$(CONFIG_LP_PCI) += pci_io_ops.c
+else
+libc-$(CONFIG_LP_PCI) += pci_map_bus_ops.c
+endif
 
 libc-$(CONFIG_LP_SPEAKER) += speaker.c
 
diff --git a/payloads/libpayload/drivers/pci_io_ops.c b/payloads/libpayload/drivers/pci_io_ops.c
new file mode 100644
index 000000000000..f6506a31ab6a
--- /dev/null
+++ b/payloads/libpayload/drivers/pci_io_ops.c
@@ -0,0 +1,67 @@
+/*
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2008 coresystems GmbH
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <libpayload.h>
+#include <pci.h>
+
+u8 pci_read_config8(pcidev_t dev, u16 reg)
+{
+	outl(dev | (reg & ~3), 0xCF8);
+	return inb(0xCFC + (reg & 3));
+}
+
+u16 pci_read_config16(pcidev_t dev, u16 reg)
+{
+	outl(dev | (reg & ~3), 0xCF8);
+	return inw(0xCFC + (reg & 3));
+}
+
+u32 pci_read_config32(pcidev_t dev, u16 reg)
+{
+	outl(dev | (reg & ~3), 0xCF8);
+	return inl(0xCFC + (reg & 3));
+}
+
+void pci_write_config8(pcidev_t dev, u16 reg, u8 val)
+{
+	outl(dev | (reg & ~3), 0xCF8);
+	outb(val, 0xCFC + (reg & 3));
+}
+
+void pci_write_config16(pcidev_t dev, u16 reg, u16 val)
+{
+	outl(dev | (reg & ~3), 0xCF8);
+	outw(val, 0xCFC + (reg & 3));
+}
+
+void pci_write_config32(pcidev_t dev, u16 reg, u32 val)
+{
+	outl(dev | (reg & ~3), 0xCF8);
+	outl(val, 0xCFC + (reg & 3));
+}
diff --git a/payloads/libpayload/drivers/pci_map_bus_ops.c b/payloads/libpayload/drivers/pci_map_bus_ops.c
new file mode 100644
index 000000000000..2b4f9d159a95
--- /dev/null
+++ b/payloads/libpayload/drivers/pci_map_bus_ops.c
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <libpayload.h>
+#include <pci.h>
+
+u8 pci_read_config8(pcidev_t dev, u16 reg)
+{
+	uintptr_t cfg_base = pci_map_bus(dev);
+
+	return read8((void *)(cfg_base | reg));
+}
+
+u16 pci_read_config16(pcidev_t dev, u16 reg)
+{
+	uintptr_t cfg_base = pci_map_bus(dev);
+
+	return read16((void *)(cfg_base | (reg & ~1)));
+}
+
+u32 pci_read_config32(pcidev_t dev, u16 reg)
+{
+	uintptr_t cfg_base = pci_map_bus(dev);
+
+	return read32((void *)(cfg_base | (reg & ~3)));
+}
+
+void pci_write_config8(pcidev_t dev, u16 reg, u8 val)
+{
+	uintptr_t cfg_base = pci_map_bus(dev);
+
+	write8((void *)(cfg_base | reg), val);
+}
+
+void pci_write_config16(pcidev_t dev, u16 reg, u16 val)
+{
+	uintptr_t cfg_base = pci_map_bus(dev);
+
+	write16((void *)(cfg_base | (reg & ~1)), val);
+}
+
+void pci_write_config32(pcidev_t dev, u16 reg, u32 val)
+{
+	uintptr_t cfg_base = pci_map_bus(dev);
+
+	write32((void *)(cfg_base | (reg & ~3)), val);
+}
diff --git a/payloads/libpayload/drivers/pci.c b/payloads/libpayload/drivers/pci_ops.c
index 90e9220d0aa4..79c3bc078131 100644
--- a/payloads/libpayload/drivers/pci.c
+++ b/payloads/libpayload/drivers/pci_ops.c
@@ -30,42 +30,6 @@
 #include <libpayload.h>
 #include <pci.h>
 
-u8 pci_read_config8(pcidev_t device, u16 reg)
-{
-	outl(device | (reg & ~3), 0xCF8);
-	return inb(0xCFC + (reg & 3));
-}
-
-u16 pci_read_config16(pcidev_t device, u16 reg)
-{
-	outl(device | (reg & ~3), 0xCF8);
-	return inw(0xCFC + (reg & 3));
-}
-
-u32 pci_read_config32(pcidev_t device, u16 reg)
-{
-	outl(device | (reg & ~3), 0xCF8);
-	return inl(0xCFC + (reg & 3));
-}
-
-void pci_write_config8(pcidev_t device, u16 reg, u8 val)
-{
-	outl(device | (reg & ~3), 0xCF8);
-	outb(val, 0xCFC + (reg & 3));
-}
-
-void pci_write_config16(pcidev_t device, u16 reg, u16 val)
-{
-	outl(device | (reg & ~3), 0xCF8);
-	outw(val, 0xCFC + (reg & 3));
-}
-
-void pci_write_config32(pcidev_t device, u16 reg, u32 val)
-{
-	outl(device | (reg & ~3), 0xCF8);
-	outl(val, 0xCFC + (reg & 3));
-}
-
 static int find_on_bus(int bus, unsigned short vid, unsigned short did,
 		       pcidev_t * dev)
 {
diff --git a/payloads/libpayload/include/pci.h b/payloads/libpayload/include/pci.h
index ce5081c48bb5..d78b8cab5e0c 100644
--- a/payloads/libpayload/include/pci.h
+++ b/payloads/libpayload/include/pci.h
@@ -31,6 +31,8 @@
 #define _PCI_H
 
 #include <arch/types.h>
+#include <stdint.h>
+
 typedef u32 pcidev_t;
 
 /* Device config space registers. */
@@ -100,13 +102,15 @@ typedef u32 pcidev_t;
 #define PCI_SLOT(_d) ((_d >> 11) & 0x1f)
 #define PCI_FUNC(_d) ((_d >> 8) & 0x7)
 
-u8 pci_read_config8(u32 device, u16 reg);
-u16 pci_read_config16(u32 device, u16 reg);
-u32 pci_read_config32(u32 device, u16 reg);
+uintptr_t pci_map_bus(pcidev_t dev);
+
+u8 pci_read_config8(pcidev_t dev, u16 reg);
+u16 pci_read_config16(pcidev_t dev, u16 reg);
+u32 pci_read_config32(pcidev_t dev, u16 reg);
 
-void pci_write_config8(u32 device, u16 reg, u8 val);
-void pci_write_config16(u32 device, u16 reg, u16 val);
-void pci_write_config32(u32 device, u16 reg, u32 val);
+void pci_write_config8(pcidev_t dev, u16 reg, u8 val);
+void pci_write_config16(pcidev_t dev, u16 reg, u16 val);
+void pci_write_config32(pcidev_t dev, u16 reg, u32 val);
 
 int pci_find_device(u16 vid, u16 did, pcidev_t *dev);
 u32 pci_read_resource(pcidev_t dev, int bar);