coreboot_tables: Add PCIe info to coreboot table

Add 'lb_fill_pcie' function to pass PCIe information from coreboot to
libpayload, and add CB_ERR_NOT_IMPLEMENTED to the cb_err enum for the
__weak function.

ARM platform usually does not have common address for PCIe to access the
configuration space of devices. Therefore, new API is added to pass the
base address of PCIe controller for payloads to access PCIe devices.

TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
 == NVME IDENTIFY CONTROLLER DATA ==
    PCI VID   : 0x15b7
    PCI SSVID : 0x15b7
    SN        : 21517J440114
    MN        : WDC PC SN530 SDBPTPZ-256G-1006
    RAB       : 0x4
    AERL      : 0x7
    SQES      : 0x66
    CQES      : 0x44
    NN        : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006

BUG=b:178565024
BRANCH=cherry

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: I6cdce21efc66aa441ec077e6fc1d5d1c6a9aafb0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>

3 files changed, 18 insertions, 0 deletions

diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h
index 1d38c19a80f1..a8fd5cd32174 100644
--- a/payloads/libpayload/include/coreboot_tables.h
+++ b/payloads/libpayload/include/coreboot_tables.h
@@ -84,6 +84,7 @@ enum {
 	CB_TAG_ACPI_CNVS		= 0x0041,
 	CB_TAG_TYPE_C_INFO		= 0x0042,
 	CB_TAG_ACPI_RSDP                = 0x0043,
+	CB_TAG_PCIE			= 0x0044,
 	CB_TAG_CMOS_OPTION_TABLE	= 0x00c8,
 	CB_TAG_OPTION			= 0x00c9,
 	CB_TAG_OPTION_ENUM		= 0x00ca,
@@ -265,6 +266,12 @@ struct cb_gpios {
 	struct cb_gpio gpios[0];
 };
 
+struct cb_pcie {
+	uint32_t tag;
+	uint32_t size;
+	cb_uint64_t ctrl_base;	/* Base address of PCIe controller */
+};
+
 struct lb_range {
 	uint32_t tag;
 	uint32_t size;
diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h
index c8c10524f4f0..12d8a13e3fb0 100644
--- a/payloads/libpayload/include/sysinfo.h
+++ b/payloads/libpayload/include/sysinfo.h
@@ -84,6 +84,7 @@ struct sysinfo_t {
 	uintptr_t linker;
 	uintptr_t assembler;
 	uintptr_t mem_chip_base;
+	uintptr_t pcie_ctrl_base; /* Base address of PCIe controller */
 
 	uintptr_t cb_version;
 
diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c
index cdd6a437b683..bcc9530733bb 100644
--- a/payloads/libpayload/libc/coreboot.c
+++ b/payloads/libpayload/libc/coreboot.c
@@ -264,6 +264,13 @@ static void cb_parse_cbmem_entry(void *ptr, struct sysinfo_t *info)
 	}
 }
 
+static void cb_parse_pcie(void *ptr, struct sysinfo_t *info)
+{
+	const struct cb_pcie *pcie = ptr;
+
+	info->pcie_ctrl_base = pcie->ctrl_base;
+}
+
 static void cb_parse_rsdp(void *ptr, struct sysinfo_t *info)
 {
 	const struct cb_acpi_rsdp *cb_acpi_rsdp = ptr;
@@ -413,6 +420,9 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 		case CB_TAG_ACPI_RSDP:
 			cb_parse_rsdp(ptr, info);
 			break;
+		case CB_TAG_PCIE:
+			cb_parse_pcie(ptr, info);
+			break;
 		default:
 			cb_parse_arch_specific(rec, info);
 			break;