This patch:

* Moves non-DRAM early init code out of initram and into stage1, where 
it should have been in the first place
* Fixes an issue with GP3 timer causing system reboot (possibly not 
present in current svn, but was present in my local copy)
* Fixes serial garbage from stage1 on jetway j7f2
* Fixes ROM mapping for flash > 512k on vt8237
* Makes a couple minor whitespace changes
* Moves some function prototypes to the headers where they belong
* Nukes some phase2 hackery that belongs in phase4 (eventually)
* Comments out early_mtrr_init() for via/epia-cn, this breaks booting on 
jetway j7f2
* Moves troublesome SATA init code into stage1 - change of device class 
hangs coreboot
* Gets to vt8237 IDE phase6 init and dies on jetway/j7f2:
	Phase 6: Initializing devices...                                                
	Phase 6: Root Device init.                                                      
	Phase 6: PCI: 00:10.1 init.                                                     
	Primary IDE interface enabled                                                   
	Secondary IDE interface enabled 
	<hang>

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1070 f3766cd6-281f-0410-b1cd-43a5c92072e9

5 files changed, 81 insertions, 9 deletions

diff --git a/southbridge/via/vt8237/ide.c b/southbridge/via/vt8237/ide.c
index 5caeb862c169..d9312cee7a0f 100644
--- a/southbridge/via/vt8237/ide.c
+++ b/southbridge/via/vt8237/ide.c
@@ -95,8 +95,8 @@ struct device_operations vt8237_ide = {
 		{.pci = {.vendor = PCI_VENDOR_ID_VIA,
 				.device = PCI_DEVICE_ID_VIA_VT8237_PATA}}},
 	.constructor			= default_device_constructor,
-	.phase2_fixup			= vt8237_enable,
-	.phase3_scan			= 0,
+	//.phase2_fixup			= vt8237_enable,
+	//.phase3_scan			= 0,
 	//.phase4_enable_disable		= vt8237_enable,
 	//.phase4_read_resources		= pci_dev_read_resources,
 	//.phase4_set_resources		= pci_set_resources,
diff --git a/southbridge/via/vt8237/lpc.c b/southbridge/via/vt8237/lpc.c
index 0fc2b9637da4..38bce0fe0a6b 100644
--- a/southbridge/via/vt8237/lpc.c
+++ b/southbridge/via/vt8237/lpc.c
@@ -448,7 +448,6 @@ struct device_operations vt8237r_lpc = {
 		{.pci = {.vendor = PCI_VENDOR_ID_VIA,
 				.device = PCI_DEVICE_ID_VIA_VT8237R_LPC}}},
 	.constructor			= default_device_constructor,
-	.phase2_fixup			= vt8237_enable,
 	.phase3_scan			= scan_static_bus,
 	.phase4_read_resources		= vt8237_read_resources,
 	.phase4_set_resources		= pci_set_resources,
@@ -461,7 +460,6 @@ struct device_operations vt8237s_lpc = {
 		{.pci = {.vendor = PCI_VENDOR_ID_VIA,
 				.device = PCI_DEVICE_ID_VIA_VT8237S_LPC}}},
 	.constructor			= default_device_constructor,
-	.phase2_fixup			= vt8237_enable,
 	.phase3_scan			= scan_static_bus,
 	.phase4_read_resources		= vt8237_read_resources,
 	.phase4_set_resources		= pci_set_resources,
diff --git a/southbridge/via/vt8237/sata.c b/southbridge/via/vt8237/sata.c
index aa976c0338d1..4d74ae4117e6 100644
--- a/southbridge/via/vt8237/sata.c
+++ b/southbridge/via/vt8237/sata.c
@@ -23,6 +23,9 @@
 #include "vt8237.h"
 
 /* TODO: use phase2_fixup to disable SATA */
+
+/* Causes coreboot to hang, so moved to stage1 code 
+   TODO: Fix vt8237s */
 static void sata_i_init(struct device *dev)
 {
 	u8 reg;
@@ -100,12 +103,12 @@ struct device_operations vt8237r_sata = {
 		{.pci = {.vendor = PCI_VENDOR_ID_VIA,
 				.device = PCI_DEVICE_ID_VIA_VT8237R_SATA}}},
 	.constructor			= default_device_constructor,
-	.phase3_scan			= 0,
+	//.phase3_scan			= 0,
 	//.phase4_enable_disable		= vt8237_enable,
 	//.phase4_read_resources		= pci_dev_read_resources,
 	//.phase4_set_resources		= pci_set_resources,
 	//.phase5_enable_resources	= pci_dev_enable_resources,
-	.phase6_init			= sata_i_init,
+	//.phase6_init			= sata_i_init,
 };
 
 struct device_operations vt8237s_sata = {
@@ -113,8 +116,7 @@ struct device_operations vt8237s_sata = {
 		{.pci = {.vendor = PCI_VENDOR_ID_VIA,
 				.device = PCI_DEVICE_ID_VIA_VT8237S_SATA}}},
 	.constructor			= default_device_constructor,
-	.phase2_fixup			= 0,
-	.phase3_scan			= 0,
+	//.phase3_scan			= 0,
 	//.phase4_enable_disable		= vt8237_enable,
 	//.phase4_read_resources		= pci_dev_read_resources,
 	//.phase4_set_resources		= pci_set_resources,
diff --git a/southbridge/via/vt8237/stage1.c b/southbridge/via/vt8237/stage1.c
index 65a6dfa7720d..f1ab6b280776 100644
--- a/southbridge/via/vt8237/stage1.c
+++ b/southbridge/via/vt8237/stage1.c
@@ -27,12 +27,13 @@
 #include <device/pci_ids.h>
 #include <spd.h>
 #include "vt8237.h"
+#include <config.h>
 
 /* TODO List:
  * * Merge the rest of the functions from v2, except smbus_fixup which doesn't
  *   seem to be necessary any more (?)
  * * Clean up vt8237_early_network_init. 
- *   Comments in code indicate that it's broken?
+ *     Comments in code indicate that it's broken?
  * * Figure out if the smbus actually needs to be reset after every transaction.
  */
 
@@ -189,6 +190,76 @@ void enable_smbus(u16 smbus_io_base)
 	inb(smbus_io_base + SMBHSTCTL);
 }
 
+/* The change from RAID to SATA in phase6 causes coreboot to lock up, so do it
+ * as early as possible. Move back to stage2 later */ 
+static void sata_stage1(void)
+{
+	u32 dev;
+	u8 reg;
+
+	pci_conf1_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_SATA, &dev);
+
+	printk(BIOS_DEBUG, "Configuring VIA SATA controller\n");
+
+	/* Class IDE Disk */
+	reg = pci_conf1_read_config8(dev, SATA_MISC_CTRL);
+	reg &= 0x7f;		/* Sub Class Write Protect off */
+	pci_conf1_write_config8(dev, SATA_MISC_CTRL, reg);
+
+	/* Change the device class to SATA from RAID. */
+	pci_conf1_write_config8(dev, PCI_CLASS_DEVICE, 0x1);
+	reg |= 0x80;		/* Sub Class Write Protect on */
+	pci_conf1_write_config8(dev, SATA_MISC_CTRL, reg);
+}
+
+void vt8237_stage1(u16 smbus_io_base)
+{
+	u32 dev;
+	u32 ide_dev;
+	
+	printk(BIOS_DEBUG, "Doing vt8237r/s stage1 init\n");
+
+	pci_conf1_find_device(0x1106, 0x3227, &dev);
+	pci_conf1_find_device(0x1106, 0x0571, &ide_dev);
+	
+	/* Disable GP3 timer, or else the system reboots when it runs out */
+	pci_conf1_write_config8(dev, 0x98, 0x00);
+	
+	/* Change the ROM size mapping based on where CAR is located */
+#if (CONFIG_CARBASE + CONFIG_CARSIZE) < 0xffc00000
+	pci_conf1_write_config8(dev, 0x41, 0x7f);
+#elif (CONFIG_CARBASE + CONFIG_CARSIZE) < 0xffe00000
+	pci_conf1_write_config8(dev, 0x41, 0x70);
+#elif (CONFIG_CARBASE + CONFIG_CARSIZE) < 0xfff00000
+	pci_conf1_write_config8(dev, 0x41, 0x40);
+#endif
+
+	pci_conf1_write_config8(dev, 0x50, 0x80);//disable mc97
+	pci_conf1_write_config8(dev, 0x51, 0x1f);
+	pci_conf1_write_config8(dev, 0x58, 0x60);
+	pci_conf1_write_config8(dev, 0x59, 0x80);
+	pci_conf1_write_config8(dev, 0x5b, 0x08);
+
+	/* Make it respond to IO space */
+	pci_conf1_write_config8(ide_dev, 0x04, 0x07);
+
+	/* Compatibility mode addresses */
+	//pci_conf1_write_config32(ide_dev, 0x10, 0);
+	//pci_conf1_write_config32(ide_dev, 0x14, 0);
+	//pci_conf1_write_config32(ide_dev, 0x18, 0);
+	//pci_conf1_write_config32(ide_dev, 0x1b, 0);
+
+	/* Native mode base address */
+	//pci_conf1_write_config32(ide_dev, 0x20, BUS_MASTER_ADDR | 1);
+
+	pci_conf1_write_config8(ide_dev, 0x40, 0x3);//was 0x3
+	pci_conf1_write_config8(ide_dev, 0x41, 0xf2);
+	pci_conf1_write_config8(ide_dev, 0x42, 0x09);
+
+	sata_stage1();
+	enable_smbus(smbus_io_base);
+}
+
 /* TODO:
  * Magic numbers -> #defines
  * fix?
diff --git a/southbridge/via/vt8237/vt8237.h b/southbridge/via/vt8237/vt8237.h
index 10668519bf91..49ab6986e4de 100644
--- a/southbridge/via/vt8237/vt8237.h
+++ b/southbridge/via/vt8237/vt8237.h
@@ -77,6 +77,7 @@ struct vt8237_network_rom {
 } __attribute__ ((packed));
 
 void enable_smbus(u16);
+void vt8237_stage1(u16);
 u8 smbus_read_byte(u16, u8, u16);
 void vt8237_enable(struct device *);