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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-06-08 08:06:06 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2022-11-13 18:48:52 +0000 |
| commit | ca5a793ec31c76b168ae2f9d2260b49c79330eb2 (patch) | |
| tree | c961f3801e9187a57fee73c00f7a5ceda4d14923 /src/Kconfig | |
| parent | 9202cab6614f8a8f8d10e4539e9f6db2546d85ec (diff) | |
| download | coreboot-ca5a793ec31c76b168ae2f9d2260b49c79330eb2.tar.gz coreboot-ca5a793ec31c76b168ae2f9d2260b49c79330eb2.tar.bz2 coreboot-ca5a793ec31c76b168ae2f9d2260b49c79330eb2.zip | |
drivers/generic/ioapic: Drop poor implementation
This disables MP table generation for the affected boards
since interrupt routing entries would now be completely missing.
The mechanism itself is flawed and redundant. The mapping
of integrated PCI devices' INTx pins to IOAPIC pins is
dependent of configuration registers and needs not appear
in the devicetree.cb files at all.
The write_smp_table implementation would skip writing
any entry delivering to destination IOAPIC ID 0. This
does not follow MP table specification.
There were duplicate calls to register_new_ioapic_gsi0(),
with another present under southbridge LPC device.
Change-Id: I383d55ba2bc0800423617215e0bfdfad5136e9ac
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69488
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/Kconfig')
| -rw-r--r-- | src/Kconfig | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/Kconfig b/src/Kconfig index 08b24371bd51..f30a1bb68336 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -795,9 +795,9 @@ config ACPI_NHLT menu "System tables" config GENERATE_MP_TABLE - prompt "Generate an MP table" if HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC + prompt "Generate an MP table" if HAVE_MP_TABLE bool - default HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC + default HAVE_MP_TABLE help Generate an MP table (conforming to the Intel MultiProcessor specification 1.4) for this board. |