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| author | Vadim Bendebury <vbendeb@chromium.org> | 2015-03-02 11:33:13 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-21 08:24:39 +0200 |
| commit | be7124ee1d5f42eee86485968374c312ef57d5a1 (patch) | |
| tree | da37271a7d44c19762460f11037f10c20fe22973 /src/arch/arm/armv7/cpu.S | |
| parent | 90fe5824b124bcb415e3535722e0653505d66cc4 (diff) | |
| download | coreboot-be7124ee1d5f42eee86485968374c312ef57d5a1.tar.gz coreboot-be7124ee1d5f42eee86485968374c312ef57d5a1.tar.bz2 coreboot-be7124ee1d5f42eee86485968374c312ef57d5a1.zip | |
armv7: preserve bootblock invocation parameter
Some platforms may pass as a parameter the maskrom or vendor startup
code information when calling the bootblock.
Make sure the bootblock startup code saves this parameter for use by
coreboot. As we don't want to touch memory before caches are
initialized, save the passed in parameter in r10 for the duration of
cache initialization.
Added warning comments to help enforcing that cache initialization
code does not touch r10.
BRANCH=storm
BUG=chrome-os-partner:30623
TEST=with the rest of the patches applied see the QCA uber-sbl report
in the coreboot console output.
Change-Id: Ic6a09e8c3cf13ac4f2d12ee91c7ab41bc9aa95da
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e41584f769eb042604883275b0d0bdfbf5b0d358
Original-Change-Id: I517a79dc95040326f46f0b80ee4e74bdddde8bf4
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/255144
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Vadim Bendebury <vbendeb@gmail.com>
Reviewed-on: http://review.coreboot.org/9842
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/arch/arm/armv7/cpu.S')
| -rw-r--r-- | src/arch/arm/armv7/cpu.S | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/arch/arm/armv7/cpu.S b/src/arch/arm/armv7/cpu.S index b7f245b85dde..6c00f625829a 100644 --- a/src/arch/arm/armv7/cpu.S +++ b/src/arch/arm/armv7/cpu.S @@ -43,6 +43,8 @@ * through the magic of double subtraction. It's quite ingenius, really. * Takes care to only use r0-r3 and ip so it's pefectly ABI-compatible without * needing to write to memory. + * + * THIS FUNCTION MUST PRESERVE THE VALUE OF r10 */ .macro dcache_apply_all crm @@ -109,6 +111,8 @@ * known state regarding caches/SCTLR. Completely cleans and invalidates * icache/dcache, disables MMU and dcache (if active), and enables unaligned * accesses, icache and branch prediction (if inactive). Clobbers r4 and r5. + * + * THIS FUNCTION MUST PRESERVE THE VALUE OF r10 */ ENTRY(arm_init_caches) /* r4: SCTLR, return address: r5 (stay valid for the whole function) */ |