ARMV7 and Google/Snow: Add exception support code to the ramstage

This is previously used exception code from libpayload.
On startup it installs and then tests an exception handler.
The test is an unaligned memory operation.

Yes, we've seen what might be exceptions in the ramstage, and
it makes sense to handle them. This code is identical in structure
and operation to the previously committed payload exception handler,
though we reserve the right to change it as circumstances require.

The remaining question is whether we need it in romstage.

Change-Id: I24484686c33c9757af8ba171ebae9773828fb69d
Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2614
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>

1 files changed, 158 insertions, 0 deletions

diff --git a/src/arch/armv7/exception.c b/src/arch/armv7/exception.c
new file mode 100644
index 000000000000..14f82163c6c3
--- /dev/null
+++ b/src/arch/armv7/exception.c
@@ -0,0 +1,158 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <console/console.h>
+#include <arch/exception.h>
+#include <stdint.h>
+
+void exception_test(void);
+
+static int test_abort;
+
+void exception_undefined_instruction(uint32_t *);
+void exception_software_interrupt(uint32_t *);
+void exception_prefetch_abort(uint32_t *);
+void exception_data_abort(uint32_t *);
+void exception_not_used(uint32_t *);
+void exception_irq(uint32_t *);
+void exception_fiq(uint32_t *);
+
+static void print_regs(uint32_t *regs)
+{
+	int i;
+	/* Don't print the link register and stack pointer since we don't have their
+	 * actual value. They are hidden by the 'shadow' registers provided
+	 * by the trap hardware.
+	 */
+	for (i = 0; i < 16; i++) {
+		if (i == 15)
+			printk(BIOS_ERR, "PC");
+		else if (i == 14)
+			continue; /* LR */
+		else if (i == 13)
+			continue; /* SP */
+		else if (i == 12)
+			printk(BIOS_ERR, "IP");
+		else
+			printk(BIOS_ERR, "R%d", i);
+		printk(BIOS_ERR, " = 0x%08x\n", regs[i]);
+	}
+}
+
+void exception_undefined_instruction(uint32_t *regs)
+{
+	printk(BIOS_ERR, "exception _undefined_instruction\n");
+	print_regs(regs);
+	die("exception");
+}
+
+void exception_software_interrupt(uint32_t *regs)
+{
+	printk(BIOS_ERR, "exception _software_interrupt\n");
+	print_regs(regs);
+	die("exception");
+}
+
+void exception_prefetch_abort(uint32_t *regs)
+{
+	printk(BIOS_ERR, "exception _prefetch_abort\n");
+	print_regs(regs);
+	die("exception");
+}
+
+void exception_data_abort(uint32_t *regs)
+{
+	if (test_abort) {
+		regs[15] = regs[0];
+		return;
+	} else {
+		printk(BIOS_ERR, "exception _data_abort\n");
+		print_regs(regs);
+	}
+	die("exception");
+}
+
+void exception_not_used(uint32_t *regs)
+{
+	printk(BIOS_ERR, "exception _not_used\n");
+	print_regs(regs);
+	die("exception");
+}
+
+void exception_irq(uint32_t *regs)
+{
+	printk(BIOS_ERR, "exception _irq\n");
+	print_regs(regs);
+	die("exception");
+}
+
+void exception_fiq(uint32_t *regs)
+{
+	printk(BIOS_ERR, "exception _fiq\n");
+	print_regs(regs);
+	die("exception");
+}
+
+static inline uint32_t get_sctlr(void)
+{
+	uint32_t val;
+	asm("mrc p15, 0, %0, c1, c0, 0" : "=r" (val));
+	return val;
+}
+
+static inline void set_sctlr(uint32_t val)
+{
+	asm volatile("mcr p15, 0, %0, c1, c0, 0" :: "r" (val));
+	asm volatile("" ::: "memory");
+}
+
+void exception_init(void)
+{
+	static const uint32_t sctlr_te = (0x1 << 30);
+	static const uint32_t sctlr_v = (0x1 << 13);
+	static const uint32_t sctlr_a = (0x1 << 1);
+
+	uint32_t sctlr = get_sctlr();
+	/* Handle exceptions in ARM mode. */
+	sctlr &= ~sctlr_te;
+	/* Set V=0 in SCTLR so VBAR points to the exception vector table. */
+	sctlr &= ~sctlr_v;
+	/* Enforce alignment. */
+	sctlr |= sctlr_a;
+	set_sctlr(sctlr);
+
+	extern uint32_t exception_table[];
+	set_vbar((uintptr_t)exception_table);
+
+	test_abort = 1;
+	printk(BIOS_ERR, "Testing exceptions\n");
+	exception_test();
+	test_abort = 0;
+	printk(BIOS_ERR, "Testing exceptions: DONE\n");
+}