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| author | Yaroslav Kurlaev <yaroslav.kurlaev@3mdeb.com> | 2021-07-06 22:38:37 +0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-11 20:17:18 +0000 |
| commit | 956a8b69d2eaaf597909ff8b5c16b87085eba440 (patch) | |
| tree | beb074bbef5841853919de58b09f52784b5fc226 /src/arch/ppc64 | |
| parent | bcbcdf73943d8bc81f2e35c4a67eebcbde716eda (diff) | |
| download | coreboot-956a8b69d2eaaf597909ff8b5c16b87085eba440.tar.gz coreboot-956a8b69d2eaaf597909ff8b5c16b87085eba440.tar.bz2 coreboot-956a8b69d2eaaf597909ff8b5c16b87085eba440.zip | |
src/mainboard/emulation/qemu-power9: require hb-mode=on
"hb-mode" is a -machine flag for QEMU. "hb" stands for Hostboot, which
is OpenPower firmware created by IBM.
QEMU for PPC64 can run initial program in two different modes:
* hb-mode=off with load address 0x00000000
* hb-mode=on with load address 0x08000000
Real hardware always loads firmware at 0x08000000 and coreboot shouldn't
require a special build to be run on QEMU.
Memory layout is updated to reflect change of load address.
Change-Id: I1bdc97a095bd46fccc862985b3bd24f4fa5bc054
Signed-off-by: Yaroslav Kurlaev <yaroslav.kurlaev@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Diffstat (limited to 'src/arch/ppc64')
| -rw-r--r-- | src/arch/ppc64/include/arch/io.h | 2 | ||||
| -rw-r--r-- | src/arch/ppc64/rom_media.c | 5 | ||||
| -rw-r--r-- | src/arch/ppc64/stages.c | 13 |
3 files changed, 17 insertions, 3 deletions
diff --git a/src/arch/ppc64/include/arch/io.h b/src/arch/ppc64/include/arch/io.h index 6dc0a84b6c16..cfaae33f600b 100644 --- a/src/arch/ppc64/include/arch/io.h +++ b/src/arch/ppc64/include/arch/io.h @@ -8,7 +8,9 @@ /* Set MSB to 1 to ignore HRMOR */ #define MMIO_GROUP0_CHIP0_LPC_BASE_ADDR 0x8006030000000000 #define LPCHC_IO_SPACE 0xD0010000 +#define FLASH_IO_SPACE 0xFC000000 #define LPC_BASE_ADDR (MMIO_GROUP0_CHIP0_LPC_BASE_ADDR + LPCHC_IO_SPACE) +#define FLASH_BASE_ADDR (MMIO_GROUP0_CHIP0_LPC_BASE_ADDR + FLASH_IO_SPACE) #define MMIO_GROUP0_CHIP0_SCOM_BASE_ADDR 0x800603FC00000000 /* Enforce In-order Execution of I/O */ diff --git a/src/arch/ppc64/rom_media.c b/src/arch/ppc64/rom_media.c index 7d849e4cdbb7..2fd47669a80e 100644 --- a/src/arch/ppc64/rom_media.c +++ b/src/arch/ppc64/rom_media.c @@ -1,11 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/io.h> #include <boot_device.h> -/* This assumes that the CBFS resides at 0x0, which is true for the default - * configuration. */ static const struct mem_region_device boot_dev = - MEM_REGION_DEV_RO_INIT(NULL, CONFIG_ROM_SIZE); + MEM_REGION_DEV_RO_INIT(FLASH_BASE_ADDR, CONFIG_ROM_SIZE); const struct region_device *boot_device_ro(void) { diff --git a/src/arch/ppc64/stages.c b/src/arch/ppc64/stages.c index 20ed723bf5af..01b9efaba8df 100644 --- a/src/arch/ppc64/stages.c +++ b/src/arch/ppc64/stages.c @@ -13,10 +13,23 @@ #include <cbmem.h> #include <arch/stages.h> +#include <cpu/power/spr.h> void stage_entry(uintptr_t stage_arg) { +#if ENV_RAMSTAGE + uint64_t hrmor; +#endif + if (!ENV_ROMSTAGE_OR_BEFORE) _cbmem_top_ptr = stage_arg; + +#if ENV_RAMSTAGE + hrmor = read_spr(SPR_HRMOR); + asm volatile("sync; isync" ::: "memory"); + write_spr(SPR_HRMOR, 0); + asm volatile("or 1,1,%0; slbia 7; sync; isync" :: "r"(hrmor) : "memory"); +#endif + main(); } |