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author | Elyes HAOUAS <ehaouas@noos.fr> | 2021-02-05 09:27:53 +0100 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-07 21:53:23 +0000 |
commit | d30d9a27dce0456e586f59f4d1add99d19c0ac35 (patch) | |
tree | 161668887b3b165d954c78b3796d803b35a6db32 /src/arch/riscv | |
parent | 996bab4a2096d47be0a60e9930f0b10d62eec5ed (diff) | |
download | coreboot-d30d9a27dce0456e586f59f4d1add99d19c0ac35.tar.gz coreboot-d30d9a27dce0456e586f59f4d1add99d19c0ac35.tar.bz2 coreboot-d30d9a27dce0456e586f59f4d1add99d19c0ac35.zip |
src: Remove redundant include <rules.h>
Change-Id: Ie4692246d059734bb5bad6c64042b64068636ab6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/arch/riscv')
-rw-r--r-- | src/arch/riscv/romstage.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/arch/riscv/romstage.c b/src/arch/riscv/romstage.c index 5146b0e55f66..c7340b2719b9 100644 --- a/src/arch/riscv/romstage.c +++ b/src/arch/riscv/romstage.c @@ -9,7 +9,6 @@ #include <arch/stages.h> #include <arch/smp/smp.h> -#include <rules.h> #include <mcall.h> void stage_entry(int hart_id, void *fdt) |