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| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-13 00:17:43 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-20 13:23:13 +0000 |
| commit | 79572e4f32f844f60338d1aafdba6b94f4111a5c (patch) | |
| tree | af087e9ff1188b68fa81db4c813adb7b5fc42287 /src/arch/x86/Makefile.inc | |
| parent | 3eb8dbaee2eac62438b6c5391c09979bcaed32b0 (diff) | |
| download | coreboot-79572e4f32f844f60338d1aafdba6b94f4111a5c.tar.gz coreboot-79572e4f32f844f60338d1aafdba6b94f4111a5c.tar.bz2 coreboot-79572e4f32f844f60338d1aafdba6b94f4111a5c.zip | |
src: Make HAVE_CF9_RESET set the FADT reset register
All supported x86 chips select HAVE_CF9_RESET, and also use 0xcf9 as
reset register in FADT. How unsurprising. We might as well use that
information to automatically fill in the FADT accordingly. So, do it.
To avoid having x86-specific code under arch-agnostic `acpi/`, create a
new optional `arch_fill_fadt` function, and override it for x86 systems.
Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.
Change-Id: Ib436b04aafd66c3ddfa205b870c1e95afb3e846d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Diffstat (limited to 'src/arch/x86/Makefile.inc')
| -rw-r--r-- | src/arch/x86/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 61e7edcfb9e5..00690ba02ee9 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -235,6 +235,7 @@ $(CONFIG_CBFS_PREFIX)/postcar-compression := none ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32)$(CONFIG_ARCH_RAMSTAGE_X86_64),y) +ramstage-y += acpi.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c ramstage-$(CONFIG_ACPI_BERT) += acpi_bert_storage.c ramstage-y += boot.c |