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| author | Aaron Durbin <adurbin@chromium.org> | 2015-09-29 14:54:25 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2015-09-30 06:53:42 +0000 |
| commit | 1bc6a79874bc464167ff27319adc16ec87a7206c (patch) | |
| tree | e6e3a5abe07d8643b8bd516e4b59874344095c29 /src/arch/x86/assembly_entry.S | |
| parent | 115360fdb36be77e86dfa1208f3c1e3dca649685 (diff) | |
| download | coreboot-1bc6a79874bc464167ff27319adc16ec87a7206c.tar.gz coreboot-1bc6a79874bc464167ff27319adc16ec87a7206c.tar.bz2 coreboot-1bc6a79874bc464167ff27319adc16ec87a7206c.zip | |
x86: provide common macro for linking early stages
In order to support verstage on x86 one needs to link verstage
like romstage since it needs all the cache-as-ram goodies. Therefore,
provide a macro that one can invoke that provides the necessary
recipes for linking that particular stage in such an environment.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados.
Change-Id: I12f4872df09fff6715829de68fc374e230350c2e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11739
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/arch/x86/assembly_entry.S')
| -rw-r--r-- | src/arch/x86/assembly_entry.S | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S new file mode 100644 index 000000000000..c23d17705294 --- /dev/null +++ b/src/arch/x86/assembly_entry.S @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* This file assembles the start of the romstage program by the order of the + * includes. Thus, it's extremely important that one pays very careful + * attention to the order of the includes. */ + +#include <arch/x86/prologue.inc> +#include <cpu/x86/32bit/entry32.inc> +#include <cpu/x86/fpu_enable.inc> +#if IS_ENABLED(CONFIG_SSE) +#include <cpu/x86/sse_enable.inc> +#endif + +/* + * The assembly.inc is generated based on the requirements of the mainboard. + * For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be + * processed by ROMCC and added. In non-ROMCC boards the chipsets' + * cache-as-ram setup files would be here. + */ +#include <generated/assembly.inc> |