summaryrefslogtreecommitdiffstats
path: root/src/arch/x86/postcar_loader.c
diff options
context:
space:
mode:
authorAaron Durbin <adurbin@chromium.org>2016-03-18 12:21:23 -0500
committerAaron Durbin <adurbin@chromium.org>2016-03-23 14:24:30 +0100
commit7f8afe063139f6fc7076a3e4edf6093a953792dc (patch)
treeb7d0c8d6372abe5b96bc37068e3e132ab97b8ea7 /src/arch/x86/postcar_loader.c
parent2b239485358ec063a4803f248c88378076810e24 (diff)
downloadcoreboot-7f8afe063139f6fc7076a3e4edf6093a953792dc.tar.gz
coreboot-7f8afe063139f6fc7076a3e4edf6093a953792dc.tar.bz2
coreboot-7f8afe063139f6fc7076a3e4edf6093a953792dc.zip
arch/x86: introduce postcar stage/phase
Certain chipsets don't have a memory-mapped boot media so their code execution for stages prior to DRAM initialization is backed by SRAM or cache-as-ram. The postcar stage/phase handles the cache-as-ram situation where in order to tear down cache-as-ram one needs to be executing out of a backing store that isn't transient. By current definition, cache-as-ram is volatile and tearing it down leads to its contents disappearing. Therefore provide a shim layer, postcar, that's loaded into memory and executed which does 2 things: 1. Tears down cache-as-ram with a chipset helper function. 2. Loads and runs ramstage. Because those 2 things are executed out of ram there's no issue of the code's backing store while executing the code that tears down cache-as-ram. The current implementation makes no assumption regarding cacheability of the DRAM itself. If the chipset code wishes to cache DRAM for loading of the postcar stage/phase then it's also up to the chipset to handle any coherency issues pertaining to cache-as-ram destruction. Change-Id: Ia58efdadd0b48f20cfe7de2f49ab462306c3a19b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14140 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/arch/x86/postcar_loader.c')
-rw-r--r--src/arch/x86/postcar_loader.c115
1 files changed, 115 insertions, 0 deletions
diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c
new file mode 100644
index 000000000000..580cc4585c85
--- /dev/null
+++ b/src/arch/x86/postcar_loader.c
@@ -0,0 +1,115 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/cpu.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
+#include <program_loading.h>
+#include <rmodule.h>
+
+static inline void stack_push(struct postcar_frame *pcf, uint32_t val)
+{
+ uint32_t *ptr;
+
+ pcf->stack -= sizeof(val);
+ ptr = (void *)pcf->stack;
+ *ptr = val;
+}
+
+int postcar_frame_init(struct postcar_frame *pcf, size_t stack_size)
+{
+ void *stack;
+ msr_t msr;
+
+ msr = rdmsr(MTRR_CAP_MSR);
+
+ stack = cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, stack_size);
+ if (stack == NULL) {
+ printk(BIOS_ERR, "Couldn't add %zd byte stack in cbmem.\n",
+ stack_size);
+ return -1;
+ }
+
+ pcf->stack = (uintptr_t)stack;
+ pcf->stack += stack_size;
+
+ pcf->upper_mask = (1 << (cpu_phys_address_size() - 32)) - 1;
+
+ pcf->max_var_mttrs = msr.lo & MTRR_CAP_VCNT;
+
+ pcf->num_var_mttrs = 0;
+
+ return 0;
+}
+
+void postcar_frame_add_mtrr(struct postcar_frame *pcf,
+ uintptr_t addr, size_t size, int type)
+{
+ size_t align;
+
+ if (pcf->num_var_mttrs >= pcf->max_var_mttrs) {
+ printk(BIOS_ERR, "No more variable MTRRs: %d\n",
+ pcf->max_var_mttrs);
+ return;
+ }
+
+ /* Determine address alignment by lowest bit set in address. */
+ align = addr & (addr ^ (addr - 1));
+
+ if (align < size) {
+ printk(BIOS_ERR, "Address (%lx) alignment (%zx) < size (%zx)\n",
+ addr, align, size);
+ size = align;
+ }
+
+ /* Push MTRR mask then base -- upper 32-bits then lower 32-bits. */
+ stack_push(pcf, pcf->upper_mask);
+ stack_push(pcf, ~(size - 1) | MTRR_PHYS_MASK_VALID);
+ stack_push(pcf, 0);
+ stack_push(pcf, addr | type);
+ pcf->num_var_mttrs++;
+}
+
+void run_postcar_phase(struct postcar_frame *pcf)
+{
+ struct prog prog =
+ PROG_INIT(PROG_UNKNOWN, CONFIG_CBFS_PREFIX "/postcar");
+ struct rmod_stage_load rsl = {
+ .cbmem_id = CBMEM_ID_AFTER_CAR,
+ .prog = &prog,
+ };
+
+ /*
+ * Place the number of used variable MTRRs on stack then max number
+ * of variable MTRRs supported in the system.
+ */
+ stack_push(pcf, pcf->num_var_mttrs);
+ stack_push(pcf, pcf->max_var_mttrs);
+
+ if (prog_locate(&prog))
+ die("Failed to locate after CAR program.\n");
+ if (rmodule_stage_load(&rsl))
+ die("Failed to load after CAR program.\n");
+
+ /* Set the stack pointer within parameters of the program loaded. */
+ if (rsl.params == NULL)
+ die("No parameters found in after CAR program.\n");
+
+ *(uintptr_t *)rsl.params = pcf->stack;
+
+ prog_run(&prog);
+}