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| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-03-30 19:34:10 +0200 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2022-04-01 13:45:07 +0000 |
| commit | 0c6298761b3800c88d781770286aea7194fd5bc0 (patch) | |
| tree | 6b43ce8a5b109b62e424251accadbc8d09bbe96e /src/arch | |
| parent | 32a1d7ea8cb6fa8d1c135af8386cf503a9337962 (diff) | |
| download | coreboot-0c6298761b3800c88d781770286aea7194fd5bc0.tar.gz coreboot-0c6298761b3800c88d781770286aea7194fd5bc0.tar.bz2 coreboot-0c6298761b3800c88d781770286aea7194fd5bc0.zip | |
arch/x86/Kconfig: Drop obsolete fixed ramstage symbols
On x86 ramstage is always relocated at runtime in cbmem so there is no
need to have this configurable in Kconfig.
Change-Id: I01b2335d0b82bea8f885ee5ca9814351bbf2aa3c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63215
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/x86/Kconfig | 16 | ||||
| -rw-r--r-- | src/arch/x86/include/arch/memlayout.h | 4 | ||||
| -rw-r--r-- | src/arch/x86/memlayout.ld | 3 |
3 files changed, 2 insertions, 21 deletions
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 4052b2e18217..e9fce5026fb4 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -118,22 +118,6 @@ config SIPI_VECTOR_IN_ROM default n depends on ARCH_X86 -# Set the rambase for systems that still need it, only 5 chipsets as of -# Sep 2018. This value was 0x100000, chosen to match the entry point -# of Linux 2.2 in 1999. The new value, 14 MiB, makes a lot more sense -# for as long as we need it; with luck, that won't be much longer. -# In the long term, both RAMBASE and RAMTOP should be removed. -# This value leaves more than 1 MiB which is required for fam10 -# and broadwell_de. -config RAMBASE - hex - default 0xe00000 - -config RAMTOP - hex - default 0x1000000 - depends on ARCH_X86 - # Traditionally BIOS region on SPI flash boot media was memory mapped right below # 4G and it was the last region in the IFD. This way translation between CPU # address space to flash address was trivial. However some IFDs on newer SoCs diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h index aea5a7ddb88d..4f5d21a5e63e 100644 --- a/src/arch/x86/include/arch/memlayout.h +++ b/src/arch/x86/include/arch/memlayout.h @@ -3,10 +3,6 @@ #ifndef __ARCH_MEMLAYOUT_H #define __ARCH_MEMLAYOUT_H -#if (CONFIG_RAMTOP == 0) -# error "CONFIG_RAMTOP not configured" -#endif - /* Intel386 psABI requires a 16 byte aligned stack. */ #define ARCH_STACK_ALIGN_SIZE 16 diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index a0b0f536ff48..bbd545005829 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -13,7 +13,8 @@ SECTIONS * conditionalize with macros. */ #if ENV_RAMSTAGE - RAMSTAGE(CONFIG_RAMBASE, 8M) + /* Relocated at runtime in cbmem so the address does not matter. */ + RAMSTAGE(64M, 8M) #elif ENV_ROMSTAGE /* The 1M size is not allocated. It's just for basic size checking. |