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| author | Jeremy Compostella <jeremy.compostella@intel.com> | 2023-09-07 10:33:30 -0700 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-09-12 08:12:02 +0000 |
| commit | 1eff77bc59b77735872e675a8df4f059245e4be7 (patch) | |
| tree | 6a09a4c448c22e5c6f97138d88526a4a00f5e971 /src/arch | |
| parent | a6a5b25ce4235c4e645d3dc20f8222b1a81c54a3 (diff) | |
| download | coreboot-1eff77bc59b77735872e675a8df4f059245e4be7.tar.gz coreboot-1eff77bc59b77735872e675a8df4f059245e4be7.tar.bz2 coreboot-1eff77bc59b77735872e675a8df4f059245e4be7.zip | |
arch/x86: Reduce max phys address size for Intel TME capable SoCs
On Intel SoCs, if TME is supported, TME key ID bits are reserved and
should be subtracted from the maximum physical addresses available.
BUG=288978352
TEST=Verified that DMAR ACPI table `Host Address Width` field on rex
went from 45 to 41.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: I9504a489782ab6ef8950a8631c269ed39c63f34d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/x86/cpu_common.c | 7 | ||||
| -rw-r--r-- | src/arch/x86/include/arch/cpu.h | 11 |
2 files changed, 16 insertions, 2 deletions
diff --git a/src/arch/x86/cpu_common.c b/src/arch/x86/cpu_common.c index e674afae306f..af4e7b001d6d 100644 --- a/src/arch/x86/cpu_common.c +++ b/src/arch/x86/cpu_common.c @@ -49,8 +49,11 @@ int cpu_phys_address_size(void) if (!(cpu_have_cpuid())) return 32; - if (cpu_cpuid_extended_level() >= 0x80000008) - return cpuid_eax(0x80000008) & 0xff; + if (cpu_cpuid_extended_level() >= 0x80000008) { + int size = cpuid_eax(0x80000008) & 0xff; + size -= get_reserved_phys_addr_bits(); + return size; + } if (cpuid_edx(1) & (CPUID_FEATURE_PAE | CPUID_FEATURE_PSE36)) return 36; diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 1355096abe2c..96cf23bb7633 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -316,4 +316,15 @@ size_t get_cache_size(const struct cpu_cache_info *info); */ bool fill_cpu_cache_info(uint8_t level, struct cpu_cache_info *info); +#if CONFIG(CPU_INTEL_COMMON) +int get_reserved_phys_addr_bits(void); +#else +/* Default implementation */ +static inline int get_reserved_phys_addr_bits(void) +{ + /* Default implementation */ + return 0; +} +#endif + #endif /* ARCH_CPU_H */ |