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| author | Aaron Durbin <adurbin@chromium.org> | 2016-07-18 00:35:42 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-07-19 20:18:08 +0200 |
| commit | 32ac01823b8345ecd6f557a439153cc2a75596a9 (patch) | |
| tree | 863aefacf526b521cb0438e1537cd1a7a709664a /src/commonlib/Makefile.inc | |
| parent | d04639b3d62dbd6a5fc7f48493411b9e74f990d1 (diff) | |
| download | coreboot-32ac01823b8345ecd6f557a439153cc2a75596a9.tar.gz coreboot-32ac01823b8345ecd6f557a439153cc2a75596a9.tar.bz2 coreboot-32ac01823b8345ecd6f557a439153cc2a75596a9.zip | |
drivers/intel/fsp2_0: load and relocate FSPS in cbmem
The FSPS component loading was just loading to any memory address
listed in the header. That could be anywhere in the address space
including ramstage itself -- let alone corrupting the OS memory on
S3 resume. Remedy this by loading and relocating FSPS into cbmem.
The UEFI 2.4 header files include path are selected to provide the
types necessary for FSP relocation.
BUG=chrome-os-partner:52679
Change-Id: Iaba103190731fc229566a3b0231cf967522040db
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15742
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: John Zhao <john.zhao@intel.com>
Diffstat (limited to 'src/commonlib/Makefile.inc')
| -rw-r--r-- | src/commonlib/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc index be22e0097d23..3c375d5674a1 100644 --- a/src/commonlib/Makefile.inc +++ b/src/commonlib/Makefile.inc @@ -12,6 +12,7 @@ smm-y += region.c postcar-y += region.c ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp_relocate.c +ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp_relocate.c bootblock-y += cbfs.c verstage-y += cbfs.c |