diff options
| author | Nick Vaccaro <nvaccaro@google.com> | 2021-10-01 13:12:59 -0700 |
|---|---|---|
| committer | Nick Vaccaro <nvaccaro@google.com> | 2021-10-04 17:12:48 +0000 |
| commit | a62b41819ceda4108b3a97cf72f55fc470347d58 (patch) | |
| tree | 43d4c2ee7badea8dcac7388d6671dbe2a0f5a211 /src/commonlib/include | |
| parent | 56da0b79ad6f3a96f5c14405d8622b7ed10aa1f2 (diff) | |
| download | coreboot-a62b41819ceda4108b3a97cf72f55fc470347d58.tar.gz coreboot-a62b41819ceda4108b3a97cf72f55fc470347d58.tar.bz2 coreboot-a62b41819ceda4108b3a97cf72f55fc470347d58.zip | |
coreboot tables: Add type-c port info to coreboot table
This change adds type-c port information for USB Type-C ports to the
coreboot table. This allows depthcharge to know the usb2 and usb3
port number assignments for each available port, as well as the SBU
and data line orientation for the board.
BUG=b:149830546
TEST='emerge-volteer coreboot chromeos-bootimage' and verify it builds
successfully. Cherry-pick CL to enable this feature for volteer,
flash and boot volteer2 to kernel, log in and check cbmem for type-c
info exported to the payload:
localhost ~ # cbmem -c | grep type-c
added type-c port0 info to cbmem: usb2:9 usb3:1 sbu:0 data:0
added type-c port1 info to cbmem: usb2:4 usb3:2 sbu:1 data:0
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Change-Id: Ice732be2fa634dbf31ec620552b383c4a5b41451
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/commonlib/include')
| -rw-r--r-- | src/commonlib/include/commonlib/cbmem_id.h | 4 | ||||
| -rw-r--r-- | src/commonlib/include/commonlib/coreboot_tables.h | 18 |
2 files changed, 21 insertions, 1 deletions
diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index d251a4e1907e..a9cf7bdcf69b 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -78,6 +78,7 @@ #define CBMEM_ID_CBFS_RW_MCACHE 0x574d5346 #define CBMEM_ID_FSP_LOGO 0x4c4f474f #define CBMEM_ID_SMM_COMBUFFER 0x53534d32 +#define CBMEM_ID_TYPE_C_INFO 0x54595045 #define CBMEM_ID_TO_NAME_TABLE \ { CBMEM_ID_ACPI, "ACPI " }, \ @@ -145,5 +146,6 @@ { CBMEM_ID_ROM3, "VGA ROM #3 "}, \ { CBMEM_ID_FMAP, "FMAP "}, \ { CBMEM_ID_CBFS_RO_MCACHE, "RO MCACHE "}, \ - { CBMEM_ID_CBFS_RW_MCACHE, "RW MCACHE "} + { CBMEM_ID_CBFS_RW_MCACHE, "RW MCACHE "}, \ + { CBMEM_ID_TYPE_C_INFO, "TYPE_C INFO"} #endif /* _CBMEM_ID_H_ */ diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index fd7461d584c5..ab8da7bf8ef2 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -84,6 +84,7 @@ enum { LB_TAG_TPM_PPI_HANDOFF = 0x003a, LB_TAG_BOARD_CONFIG = 0x0040, LB_TAG_ACPI_CNVS = 0x0041, + LB_TAG_TYPE_C_INFO = 0x0042, /* The following options are CMOS-related */ LB_TAG_CMOS_OPTION_TABLE = 0x00c8, LB_TAG_OPTION = 0x00c9, @@ -421,6 +422,23 @@ struct lb_mmc_info { int32_t early_cmd1_status; }; +/* + * USB Type-C Port Information + * This record contains board-specific type-c port information. + * There will be one record per type-C port. + */ +struct type_c_port_info { + uint8_t usb2_port_number; + uint8_t usb3_port_number; + uint8_t sbu_orientation; + uint8_t data_orientation; +}; + +struct type_c_info { + uint32_t port_count; + struct type_c_port_info port_info[0]; +}; + struct lb_macs { uint32_t tag; uint32_t size; |