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| author | Furquan Shaikh <furquan@google.com> | 2021-06-17 22:14:13 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2021-06-18 18:38:14 +0000 |
| commit | bda86bd4974ceb279392711617eec48f37306717 (patch) | |
| tree | 708fef5d07d0b25d49b030afe7cf91b83577ceb0 /src/commonlib/include | |
| parent | 5f2141519ba6e7855d1b2e520fa23b9176394462 (diff) | |
| download | coreboot-bda86bd4974ceb279392711617eec48f37306717.tar.gz coreboot-bda86bd4974ceb279392711617eec48f37306717.tar.bz2 coreboot-bda86bd4974ceb279392711617eec48f37306717.zip | |
nvs: Add Chrome OS NVS (CNVS) information to coreboot tables
CB:51638 separated Chrome OS NVS from global NVS by allocating it
separately in CBMEM. CNVS is used in depthcharge to fill firmware
information at boot time. Thus, location of CNVS needs to be shared in
coreboot tables for depthcharge to use.
This change adds a new coreboot table tag
`CB_TAG_ACPI_CNVS`/`CB_TAG_ACPI_CNVS`(0x41) which provides the
location of CNVS in CBMEM to payload (depthcharge).
Additionally, CB:51639 refactored device nvs(DNVS) and moved it to the
end of GNVS instead of the fixed offset 0x1000. DNVS is used on older
Intel platforms like baytrail, braswell and broadwell and depthcharge
fills this at boot time as well. Since DNVS is no longer used on any
new platforms, this information is not passed in coreboot
tables. Instead depthcharge is being updated to use statically defined
offsets for DNVS.
BUG=b:191324611, b:191324611
TEST=Verified that `crossystem fwid` which reads fwid information from
CNVS is reported correctly on brya.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I3815d5ecb5f0b534ead61836c2d275083e397ff0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55665
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/commonlib/include')
| -rw-r--r-- | src/commonlib/include/commonlib/coreboot_tables.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index be40c3818f1d..fd7461d584c5 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -83,6 +83,7 @@ enum { LB_TAG_SMMSTOREV2 = 0x0039, LB_TAG_TPM_PPI_HANDOFF = 0x003a, LB_TAG_BOARD_CONFIG = 0x0040, + LB_TAG_ACPI_CNVS = 0x0041, /* The following options are CMOS-related */ LB_TAG_CMOS_OPTION_TABLE = 0x00c8, LB_TAG_OPTION = 0x00c9, |