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| author | Raul E Rangel <rrangel@chromium.org> | 2021-07-23 16:43:18 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-11-04 10:33:52 +0000 |
| commit | 5ac82dcc20678629f2dd5497d9b657bcfa7acdf2 (patch) | |
| tree | 2e3b37072907c6683f732f22ecfe8f50bebed378 /src/commonlib/mem_pool.c | |
| parent | 533fc4dfb155bb45e8da279e1b85b676e3f6c58c (diff) | |
| download | coreboot-5ac82dcc20678629f2dd5497d9b657bcfa7acdf2.tar.gz coreboot-5ac82dcc20678629f2dd5497d9b657bcfa7acdf2.tar.bz2 coreboot-5ac82dcc20678629f2dd5497d9b657bcfa7acdf2.zip | |
commonlib/mem_pool: Allow configuring the alignment
AMD platforms require the destination to be 64 byte aligned in order to
use the SPI DMA controller. This is enforced by the destination address
register because the first 6 bits are marked as reserved.
This change adds an option to the mem_pool so the alignment can be
configured.
BUG=b:179699789
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8d77ffe4411f86c54450305320c9f52ab41a3075
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56580
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/commonlib/mem_pool.c')
| -rw-r--r-- | src/commonlib/mem_pool.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/commonlib/mem_pool.c b/src/commonlib/mem_pool.c index c300c65d6e62..d82ab18bd796 100644 --- a/src/commonlib/mem_pool.c +++ b/src/commonlib/mem_pool.c @@ -7,8 +7,11 @@ void *mem_pool_alloc(struct mem_pool *mp, size_t sz) { void *p; - /* Make all allocations be at least 8 byte aligned. */ - sz = ALIGN_UP(sz, 8); + if (mp->alignment == 0) + return NULL; + + /* We assume that mp->buf started mp->alignment aligned */ + sz = ALIGN_UP(sz, mp->alignment); /* Determine if any space available. */ if ((mp->size - mp->free_offset) < sz) |