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| author | Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> | 2019-03-14 23:23:22 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-25 11:03:13 +0000 |
| commit | 2de19038beffa154eefe40755b607aa9f94d9f9f (patch) | |
| tree | 46d9927c074aadbc2b58d10e20b3ae29d57f619a /src/commonlib/storage | |
| parent | c53e6ed62f36b8532306815b1258a337650a3d1d (diff) | |
| download | coreboot-2de19038beffa154eefe40755b607aa9f94d9f9f.tar.gz coreboot-2de19038beffa154eefe40755b607aa9f94d9f9f.tar.bz2 coreboot-2de19038beffa154eefe40755b607aa9f94d9f9f.zip | |
soc/intel/cannonlake: Clear PMCON status bits
The prev_sleep_state value was showing 5 even after warm reboot, once the
SUS_PWR_FLR bit is being set. This bit was not being cleared.
Hence clearing the PMCON status bits.
BUG=b:128482282
BRANCH=None
TEST=In cbmem logs, check for value of “prev_sleep_state” using command
cbmem –c | grep “prev_sleep_state”
For cold reboot, "prev_sleep_state 5"
For warm reboot, "prev_sleep_state 0"
Change-Id: If9863d52ed3c61b6a160df53f023b0787eaaed68
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Diffstat (limited to 'src/commonlib/storage')
0 files changed, 0 insertions, 0 deletions