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| author | Martin Roth <gaumless@gmail.com> | 2022-12-31 18:27:22 -0700 |
|---|---|---|
| committer | Elyes Haouas <ehaouas@noos.fr> | 2023-02-07 10:53:34 +0000 |
| commit | 0d34a50a360228138ade623e799b03eaba83b0a5 (patch) | |
| tree | f7091f1c391332e86cd2d9da9e84c40153d95c65 /src/commonlib | |
| parent | a891f71ad54898712e3f4228afcd05169cebb784 (diff) | |
| download | coreboot-0d34a50a360228138ade623e799b03eaba83b0a5.tar.gz coreboot-0d34a50a360228138ade623e799b03eaba83b0a5.tar.bz2 coreboot-0d34a50a360228138ade623e799b03eaba83b0a5.zip | |
src: Move POST_BOOTBLOCK_CAR to common postcodes and use it
This moves the definition for POST_BOOTBLOCK_CAR from the intel-specific
postcodes into the common postcode list, and uses it for the
cache-as-RAM init as needed.
Because POST_BOOTBLOCK_CAR was set to 0x20 in some spots and 0x21 in
most of the others, the values were consolidated into 0x21. This will
change the value on some platforms.
Any conflicts should get sorted out later in the conversion process.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8527334e679a23006b77a5645f919aea76dd4926
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Diffstat (limited to 'src/commonlib')
| -rw-r--r-- | src/commonlib/include/commonlib/console/post_codes.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/commonlib/include/commonlib/console/post_codes.h b/src/commonlib/include/commonlib/console/post_codes.h index ef296bda4961..a8a8d953f680 100644 --- a/src/commonlib/include/commonlib/console/post_codes.h +++ b/src/commonlib/include/commonlib/console/post_codes.h @@ -72,6 +72,12 @@ #define POST_ENTRY_C_START 0x13 /** + * \brief Entry into bootblock cache-as-RAM code + * + */ +#define POST_BOOTBLOCK_CAR 0x21 + +/** * \brief Entry into pci_scan_bus * * Entered pci_scan_bus() |