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| author | Martin Roth <gaumless@gmail.com> | 2022-11-03 18:20:17 -0600 |
|---|---|---|
| committer | Fred Reitberger <reitbergerfred@gmail.com> | 2022-11-08 14:51:02 +0000 |
| commit | 37ccb2ce82d1c4782356a569737dd72bf9478db0 (patch) | |
| tree | 87627e6332e763b55f03e2d87f78fc325d0e73be /src/commonlib | |
| parent | 605f793af84733eda416533ccf5b220c0f5a171b (diff) | |
| download | coreboot-37ccb2ce82d1c4782356a569737dd72bf9478db0.tar.gz coreboot-37ccb2ce82d1c4782356a569737dd72bf9478db0.tar.bz2 coreboot-37ccb2ce82d1c4782356a569737dd72bf9478db0.zip | |
arch/x86 & commonlib: Add macros for postcodes used in x86/tables
The 0x9a, 0x9b, and 0x9c postcodes are not used anywhere else in the
coreboot tree other than in arch/x86/tables.c. Add macros to
standardize these postcodes.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I16be65ffa3f0b253fe4a9bb7bfb97597a760ad3f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Diffstat (limited to 'src/commonlib')
| -rw-r--r-- | src/commonlib/include/commonlib/console/post_codes.h | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/src/commonlib/include/commonlib/console/post_codes.h b/src/commonlib/include/commonlib/console/post_codes.h index 8b154caeb586..8ab069bf1c1f 100644 --- a/src/commonlib/include/commonlib/console/post_codes.h +++ b/src/commonlib/include/commonlib/console/post_codes.h @@ -287,6 +287,27 @@ #define POST_FSP_SILICON_EXIT 0x99 /** + * \brief Entry to write_pirq_table + * + * coreboot entered write_pirq_table + */ +#define POST_X86_WRITE_PIRQ_TABLE 0x9a + +/** + * \brief Entry to write_mptable + * + * coreboot entered write_mptable + */ +#define POST_X86_WRITE_MPTABLE 0x9b + +/** + * \brief Entry to write_acpi_table + * + * coreboot entered write_acpi_table + */ +#define POST_X86_WRITE_ACPITABLE 0x9c + +/** * \brief Before calling FSP Multiphase SiliconInit * * Going to call into FSP binary for Multiple phase SI Init |