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| author | Jianjun Wang <jianjun.wang@mediatek.com> | 2022-03-31 15:34:34 +0800 |
|---|---|---|
| committer | Shelley Chen <shchen@google.com> | 2022-05-19 16:34:55 +0000 |
| commit | d16c2aa6de75fb5f0bc4d73e77891461c6977968 (patch) | |
| tree | 51e99f00f4647c976257500f0e2be903f352a883 /src/commonlib | |
| parent | cd259cb08a99812082f8bb2f7ecd23c031bb4e2d (diff) | |
| download | coreboot-d16c2aa6de75fb5f0bc4d73e77891461c6977968.tar.gz coreboot-d16c2aa6de75fb5f0bc4d73e77891461c6977968.tar.bz2 coreboot-d16c2aa6de75fb5f0bc4d73e77891461c6977968.zip | |
coreboot_tables: Add PCIe info to coreboot table
Add 'lb_fill_pcie' function to pass PCIe information from coreboot to
libpayload, and add CB_ERR_NOT_IMPLEMENTED to the cb_err enum for the
__weak function.
ARM platform usually does not have common address for PCIe to access the
configuration space of devices. Therefore, new API is added to pass the
base address of PCIe controller for payloads to access PCIe devices.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
BRANCH=cherry
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: I6cdce21efc66aa441ec077e6fc1d5d1c6a9aafb0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Diffstat (limited to 'src/commonlib')
| -rw-r--r-- | src/commonlib/bsd/include/commonlib/bsd/cb_err.h | 7 | ||||
| -rw-r--r-- | src/commonlib/include/commonlib/coreboot_tables.h | 9 |
2 files changed, 13 insertions, 3 deletions
diff --git a/src/commonlib/bsd/include/commonlib/bsd/cb_err.h b/src/commonlib/bsd/include/commonlib/bsd/cb_err.h index eec44f2f1c81..725882c60273 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cb_err.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cb_err.h @@ -13,9 +13,10 @@ * success. Allocate a new group or errors every 100 values. */ enum cb_err { - CB_SUCCESS = 0, /**< Call completed successfully */ - CB_ERR = -1, /**< Generic error code */ - CB_ERR_ARG = -2, /**< Invalid argument */ + CB_SUCCESS = 0, /**< Call completed successfully */ + CB_ERR = -1, /**< Generic error code */ + CB_ERR_ARG = -2, /**< Invalid argument */ + CB_ERR_NOT_IMPLEMENTED = -3, /**< Function not implemented */ /* NVRAM/CMOS errors */ CB_CMOS_OTABLE_DISABLED = -100, /**< Option table disabled */ diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 7666588cf65e..3f7ff2df29ac 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -86,6 +86,7 @@ enum { LB_TAG_ACPI_CNVS = 0x0041, LB_TAG_TYPE_C_INFO = 0x0042, LB_TAG_ACPI_RSDP = 0x0043, + LB_TAG_PCIE = 0x0044, /* The following options are CMOS-related */ LB_TAG_CMOS_OPTION_TABLE = 0x00c8, LB_TAG_OPTION = 0x00c9, @@ -144,6 +145,14 @@ struct lb_memory { struct lb_memory_range map[0]; }; +struct lb_pcie { + uint32_t tag; + uint32_t size; + lb_uint64_t ctrl_base; /* Base address of PCIe controller */ +}; +_Static_assert(_Alignof(struct lb_pcie) == 4, + "lb_uint64_t alignment doesn't work as expected for struct lb_pcie!"); + struct lb_hwrpb { uint32_t tag; uint32_t size; |