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| author | Subrata Banik <subratabanik@google.com> | 2023-04-14 01:31:29 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-04-21 17:22:00 +0000 |
| commit | fc313d655fa1074ad68c48dd4eec3ecb607ea003 (patch) | |
| tree | 5e023ced968e55c7e875aaf27259e5b03857eb5d /src/commonlib | |
| parent | 4b94f1dc874af4c851db28b70a0e0330748f2f08 (diff) | |
| download | coreboot-fc313d655fa1074ad68c48dd4eec3ecb607ea003.tar.gz coreboot-fc313d655fa1074ad68c48dd4eec3ecb607ea003.tar.bz2 coreboot-fc313d655fa1074ad68c48dd4eec3ecb607ea003.zip | |
{commonlib, soc/intel/cmn/cse}: Store CSE firmware version into CBMEM
The patch implements an API that stores the CSE firmware version in the
CBMEM table. The API will be called from RAMSTAGE based on boot state
machine BS_PRE_DEVICE/BS_ON_EXIT
Additionally, renamed ramstage_cse_fw_sync() to ramstage_cse_misc_ops()
in order to add more CSE related operations at ramstage.
This patch also adds a configuration option,
'SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION', which enables the storage
of firmware version information in CBMEM memory. This information can be
used to identify the firmware version that is currently installed on the
system. The option depends on the `DRIVERS_INTEL_ISH` config and
platform should be flexible enough to opt out from enabling this
feature.
The cost of sending HECI command to read the CSE FPT is significant
(~200ms) hence, the idea is to read the CSE RW version on every cold
reset (to cover the CSE update scenarios) and store into CBMEM to
avoid the cost of resending the HECI command in all consecutive warm
boots.
Later boot stages can just read the CBMEM ID to retrieve the ISH
version if required.
Finally, ensure this feature is platform specific hence, getting
enabled for the platform that would like to store the ISH version into
the CBMEM and parse to perform some additional work.
BUG=b:273661726
TEST=Able to build and boot google/marasov.
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I923049d2f1f589f87e1a29e1ac94af7f5fccc2c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/commonlib')
| -rw-r--r-- | src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h index fa5c8d9e94b4..4162d84c73b3 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h @@ -85,6 +85,7 @@ #define CBMEM_ID_MEM_CHIP_INFO 0x5048434D #define CBMEM_ID_AMD_STB 0x5f425453 #define CBMEM_ID_AMD_MP2 0x5f32504d +#define CBMEM_ID_CSE_PARTITION_VERSION 0x43535056 #define CBMEM_ID_TO_NAME_TABLE \ { CBMEM_ID_ACPI, "ACPI " }, \ @@ -163,5 +164,6 @@ { CBMEM_ID_TYPE_C_INFO, "TYPE_C INFO"},\ { CBMEM_ID_MEM_CHIP_INFO, "MEM CHIP INFO"},\ { CBMEM_ID_AMD_STB, "AMD STB"},\ - { CBMEM_ID_AMD_MP2, "AMD MP2 BUFFER"} + { CBMEM_ID_AMD_MP2, "AMD MP2 BUFFER"},\ + { CBMEM_ID_CSE_PARTITION_VERSION, "CSE PARTITION VERSION"} #endif /* _CBMEM_ID_H_ */ |