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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-12-26 19:33:28 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-12-30 21:33:26 +0000 |
| commit | 3521e260e3477b3c49835eb2330671e0bc7abe65 (patch) | |
| tree | 6b58e7e6268866396c3dd6932bf03e63319770c0 /src/console/init.c | |
| parent | fb25f9fa05751163fef2a4dabea03f07f91fdbb0 (diff) | |
| download | coreboot-3521e260e3477b3c49835eb2330671e0bc7abe65.tar.gz coreboot-3521e260e3477b3c49835eb2330671e0bc7abe65.tar.bz2 coreboot-3521e260e3477b3c49835eb2330671e0bc7abe65.zip | |
device/pci_early: Fixes for __SIMPLE_DEVICE__
The feature is used to enable PCI MMIO accesses behind
PCIe links (or bridges) before PCI enumeration has been
completed.
Add the feature for bootblock, verstage and postcar, it
is required with add-on PCIe serial cards for early
console output. It's up to the board specific code to
configure PCIe root port prior to calling console_init()
for this to work.
Remove feature from ramstage, it bypasses any resource
allocations and bus number assignments.
For the moment PCI configuration support before ramstage
is available only on ARCH_X86.
Also switch from device_t to pci_devfn_t.
Change-Id: I08acec68b6f17f4d73d30039cc41274492ea4f45
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/console/init.c')
| -rw-r--r-- | src/console/init.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/console/init.c b/src/console/init.c index 8f71b098817e..f35dd51beb2d 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -72,8 +72,9 @@ asmlinkage void console_init(void) { init_log_level(); -#if IS_ENABLED(CONFIG_EARLY_PCI_BRIDGE) && !defined(__SMM__) - pci_early_bridge_init(); +#if IS_ENABLED(CONFIG_EARLY_PCI_BRIDGE) + if (!ENV_SMM && !ENV_RAMSTAGE) + pci_early_bridge_init(); #endif console_hw_init(); |