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| author | Raul E Rangel <rrangel@chromium.org> | 2021-11-19 11:38:35 -0700 |
|---|---|---|
| committer | Raul Rangel <rrangel@chromium.org> | 2021-11-29 20:39:32 +0000 |
| commit | 4b5a490b6f3faffe1880c731b50d1a4adabfb622 (patch) | |
| tree | 09be3f175073c57db3fb02d174e6d20950979e21 /src/cpu/Makefile.inc | |
| parent | 6b446b991b00c44902b70d86c75b23a8f93d510b (diff) | |
| download | coreboot-4b5a490b6f3faffe1880c731b50d1a4adabfb622.tar.gz coreboot-4b5a490b6f3faffe1880c731b50d1a4adabfb622.tar.bz2 coreboot-4b5a490b6f3faffe1880c731b50d1a4adabfb622.zip | |
src/cpu,soc/amd/common/block/cpu: Add preload_microcode
This will enable preloading the microcode. By preloading the
file, into cbfs_cache we reduce boot time.
BUG=b:179699789
TEST=Boot guybrush with CL chain and see microcode preloading and a
reduction of 1 ms.
| 112 - started reading uCode | 1.041 | 1.204 Δ( 0.16, 0.01%) |
| 113 - finished reading uCode | 1.365 | 0.011 Δ( -1.35, -0.10%) |
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: If0c634c692c97769e71acd1175fc464dc592c356
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/cpu/Makefile.inc')
| -rw-r--r-- | src/cpu/Makefile.inc | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index ec2f19fd18d9..9f1e6c4bf526 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -56,7 +56,12 @@ $(obj)/cpu_microcode_blob.bin: $$(wildcard $$(cpu_microcode_bins)) cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin cpu_microcode_blob.bin-type := microcode +# The AMD LPC SPI DMA controller requires source files to be 64 byte aligned. +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA),y) +cpu_microcode_blob.bin-align := 64 +else cpu_microcode_blob.bin-align := 16 +endif ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),) cpu_microcode_blob.bin-COREBOOT-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC) |