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| author | Paul Menzel <paulepanter@users.sourceforge.net> | 2017-02-27 01:26:42 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-03-10 11:06:56 +0100 |
| commit | 22f32c723cf18af713d2763722e8a54779e859d9 (patch) | |
| tree | d1898644a9a1ce0877375fe73ff3a05bfd3f9d2b /src/cpu/amd/agesa/family14/model_14_init.c | |
| parent | dd6f75ae6e5b3dade912dc132b393934062c6e0e (diff) | |
| download | coreboot-22f32c723cf18af713d2763722e8a54779e859d9.tar.gz coreboot-22f32c723cf18af713d2763722e8a54779e859d9.tar.bz2 coreboot-22f32c723cf18af713d2763722e8a54779e859d9.zip | |
cpu/amd/agesa: Unify init files
The init files for the AMD families using the AGESA platform
initialization code are quite similar. So reduce the differences, by
using the same comments, variable names, console messages, and blank
lines.
Change-Id: Id4a3a5c3812a34627d726cdcbe8f4781a14be724
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/18507
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/cpu/amd/agesa/family14/model_14_init.c')
| -rw-r--r-- | src/cpu/amd/agesa/family14/model_14_init.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index 5e8c9de44b55..ecf1cfb96803 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -34,8 +34,9 @@ static void model_14_init(device_t dev) { - u32 i; + u8 i; msr_t msr; + int msrno; #if IS_ENABLED(CONFIG_LOGICAL_CPUS) u32 siblings; #endif @@ -58,11 +59,11 @@ static void model_14_init(device_t dev) /* Set shadow WB, RdMEM, WrMEM */ msr.lo = msr.hi = 0; wrmsr (0x259, msr); - msr.hi = msr.lo = 0x1e1e1e1e; + msr.lo = msr.hi = 0x1e1e1e1e; wrmsr(0x250, msr); wrmsr(0x258, msr); - for (i = 0x268; i <= 0x26f; i++) - wrmsr(i, msr); + for (msrno = 0x268; msrno <= 0x26f; i++) + wrmsr(msrno, msr); msr = rdmsr(SYSCFG_MSR); msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; @@ -97,6 +98,7 @@ static void model_14_init(device_t dev) msr.hi |= 1 << (33 - 32); wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); } + printk(BIOS_DEBUG, "siblings = %02d, ", siblings); #endif /* DisableCf8ExtCfg */ @@ -108,8 +110,6 @@ static void model_14_init(device_t dev) msr = rdmsr(HWCR_MSR); msr.lo |= (1 << 0); wrmsr(HWCR_MSR, msr); - - printk(BIOS_SPEW, "%s done.\n", __func__); } static struct device_operations cpu_dev_ops = { |