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| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-05-31 18:53:47 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-07-13 14:56:38 +0000 |
| commit | 7ae8fa538e2aaabb5414e5e90584f9bcb7e6f1e4 (patch) | |
| tree | 0368badff02dd61d7eecdc98591681e6e7990fac /src/cpu/amd/pi/00730F01/model_16_init.c | |
| parent | b00ba8c2473af6eae246de699886597e898c714b (diff) | |
| download | coreboot-7ae8fa538e2aaabb5414e5e90584f9bcb7e6f1e4.tar.gz coreboot-7ae8fa538e2aaabb5414e5e90584f9bcb7e6f1e4.tar.bz2 coreboot-7ae8fa538e2aaabb5414e5e90584f9bcb7e6f1e4.zip | |
cpu/amd: Add common helpers for TSEG and SMM
Change-Id: I73174766980e0405e7b8efd4f059bb400c0c0a25
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/cpu/amd/pi/00730F01/model_16_init.c')
| -rw-r--r-- | src/cpu/amd/pi/00730F01/model_16_init.c | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c index 1a9a2e3a639a..a33b5f35b565 100644 --- a/src/cpu/amd/pi/00730F01/model_16_init.c +++ b/src/cpu/amd/pi/00730F01/model_16_init.c @@ -1,16 +1,17 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <amdblocks/smm.h> #include <commonlib/helpers.h> #include <console/console.h> #include <cpu/amd/microcode.h> -#include <cpu/x86/msr.h> #include <cpu/amd/msr.h> -#include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> -#include <device/device.h> -#include <device/pci.h> #include <cpu/cpu.h> #include <cpu/x86/cache.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <device/device.h> +#include <device/pci.h> #include <smp/node.h> static void model_16_init(struct device *dev) @@ -44,9 +45,7 @@ static void model_16_init(struct device *dev) wrmsr(NB_CFG_MSR, msr); /* Write protect SMM space with SMMLOCK. */ - msr = rdmsr(HWCR_MSR); - msr.lo |= (1 << 0); - wrmsr(HWCR_MSR, msr); + lock_smm(); amd_update_microcode_from_cbfs(); |