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| author | Martin Roth <gaumless@gmail.com> | 2022-11-20 19:32:51 -0700 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2022-11-23 03:47:18 +0000 |
| commit | c87ab01c2d2e70c64d88d3afd4d49a0687b05b3c (patch) | |
| tree | acb2ec7d48f9600b787b0a1cdd528a5e5e20e630 /src/cpu/intel/car/p3/cache_as_ram.S | |
| parent | 4911942e949f40d0da0ed7debeadef1f3eccf17c (diff) | |
| download | coreboot-c87ab01c2d2e70c64d88d3afd4d49a0687b05b3c.tar.gz coreboot-c87ab01c2d2e70c64d88d3afd4d49a0687b05b3c.tar.bz2 coreboot-c87ab01c2d2e70c64d88d3afd4d49a0687b05b3c.zip | |
cpu/intel/car: Define post codes
This moves a lot of post code values, but unifies them between
platforms, so that the same value means the same thing as much as
possible.
The P4-netburst code was the most extensive and most different, so that
dictated the majority of the values. Three were two values there that
didn't match the other files, so those two values, 0x22 & 0x29 have
duplicate entries in the table.
The rest of the entries are similar between platforms, though the values
for many of them were moved to match the P4-netburst values.
POST_BOOTBLOCK and POST_POSTCAR values are intended to eventually become
global, while POST_SOC would be specific to the Intel platforms.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If13e40b700a41d56bca85510d68da0ab31a235a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69866
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/intel/car/p3/cache_as_ram.S')
| -rw-r--r-- | src/cpu/intel/car/p3/cache_as_ram.S | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S index 887bb22477d9..c19fa3cf6cc7 100644 --- a/src/cpu/intel/car/p3/cache_as_ram.S +++ b/src/cpu/intel/car/p3/cache_as_ram.S @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <cpu/intel/post_codes.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> @@ -13,7 +14,7 @@ _cache_as_ram_setup: bootblock_pre_c_entry: cache_as_ram: - post_code(0x20) + post_code(POST_BOOTBLOCK_CAR) /* Clear/disable fixed MTRRs */ mov $fixed_mtrr_list_size, %ebx @@ -41,7 +42,7 @@ clear_var_mtrr: inc %ecx dec %ebx jnz clear_var_mtrr - post_code(0x21) + post_code(POST_SOC_SET_DEF_MTRR_TYPE) /* Configure the default memory type to uncacheable. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -49,7 +50,7 @@ clear_var_mtrr: andl $(~0x00000cff), %eax wrmsr - post_code(0x22) + post_code(POST_SOC_DETERMINE_CPU_ADDR_BITS) /* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */ movl $1, %eax @@ -67,7 +68,7 @@ addrsize_set_high: movl $MTRR_PHYS_MASK(1), %ecx wrmsr - post_code(0x2a) + post_code(POST_SOC_SET_CAR_BASE) /* Set Cache-as-RAM base address. */ movl $(MTRR_PHYS_BASE(0)), %ecx @@ -83,7 +84,7 @@ addrsize_set_high: orl $MTRR_PHYS_MASK_VALID, %eax wrmsr - post_code(0x2b) + post_code(POST_SOC_ENABLE_MTRRS) /* Enable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -91,7 +92,7 @@ addrsize_set_high: orl $MTRR_DEF_TYPE_EN, %eax wrmsr - post_code(0x2c) + post_code(POST_SOC_ENABLE_CACHE) /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax @@ -113,7 +114,7 @@ addrsize_set_high: xorl %eax, %eax rep stosl - post_code(0x2d) + post_code(POST_SOC_DISABLE_CACHE) /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax @@ -132,7 +133,7 @@ addrsize_set_high: orl $MTRR_PHYS_MASK_VALID, %eax wrmsr - post_code(0x2e) + post_code(POST_SOC_FILL_CACHE) /* Enable cache. */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax @@ -155,7 +156,7 @@ addrsize_set_high: pushl %eax /* tsc[31:0] */ before_c_entry: - post_code(0x29) + post_code(POST_BOOTBLOCK_BEFORE_C_ENTRY) call bootblock_c_entry_bist /* Should never see this postcode */ |