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authorJeremy Compostella <jeremy.compostella@intel.com>2025-01-13 13:20:12 -0800
committerJérémy Compostella <jeremy.compostella@intel.com>2025-04-28 15:51:03 +0000
commitaafcb01ec42ca099a9b82f88c32638b3bb625f7e (patch)
treeb51ec71c6f3b70e6f54ca0bdaa9324f1fe302cd9 /src/cpu/intel/common/hyperthreading.c
parenteffd1ffdad73e23e23ffbab8fbd0f7de052126ff (diff)
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mb/intel/ptlrvp: Synchronize codebase with fatcat
This commit imports changes from mb/google/fatcat to mb/intel/ptlrvp as of coreboot codebase commit 010cfa28421b ("doc/internals/devicetree_language: multiple segment groups supported"). Here is the list of imported commits: - commit 9495063993e3 ("mainboard/google/fatcat: Fix SMBIOS Processor upgrade info") - commit 27f3427f4a1d ("mb/google/fatcat/var/fatcat: Update GSPI0 CS pin for FPS") - commit c41af2d43c49 ("mb/google/fatcat/var/fatcat: Update THC Interrupt for Touchpad Development") - commit b5dea9fa999a ("mb/google/fatcat/var/francka: Add Write Protect GPIO to cros_gpios") - commit ef80ccbc4364 ("mb/google/fatcat: Disable EC software sync for Microchip EC") - commit 9f39d6ec5e9f ("mb/google/fatcat: Enable HAVE_SLP_S0_GATE for felino and francka") - commit eb85dfae1f23 ("mb/google/fatcat: Configure GPIO_SLP_S0_GATE for francka and felino") - commit 0fc2422e88dc ("mb/google/fatcat: Implement S0ix hooks aka `MS0X` method") - commit 1fa5ab805bb1 ("mb/google/fatcat: Remove unnecessary CNVi core variables settings") - commit 5c0340349ecb ("mb/google/fatcat: Rationalize Wi-Fi and Bluetooth combinations") - commit 275beb93db80 ("mb/google/fatcat: Conditionally check for barrel charger") - commit e9b020f02e3a ("mb/google/fatcat: Allow board-specific FSP-M UPD override") - commit 3a88eb8cb6c6 ("mb/google/fatcat: Enable HDA SDI based on FW config") - commit 0ac2058dbee6 ("mb/google/fatcat: Increase sagv_freq_mhz for work point #1 to #3") - commit 6e529e7c0611 ("mb/google/fatcat: Add Intel Touch support for touchscreen and touchpad") Overall, these commits aim to improve the configuration, performance, and compatibility of the Intel Panther Lake Reference Validation Platform (PTLRVP) mainboard across various aspects, including processor upgrade support, peripheral integration, power management, and audio functionality. TEST=Successful boot with a ptlrvp image on a Fatcat board. Change-Id: Ie27763a367d8d53c64ad78d26909f1068af3c819 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87223 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Zhixing Ma <zhixing.ma@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/intel/common/hyperthreading.c')
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